Abstract: A method for providing, based on an emulation schedule, a reset message to multiple circuits is provided. The reset message associates a reset signal with a selected clock cycle for each circuit, in the emulation schedule. The method includes determining a mask for each of the circuits based on the emulation schedule, providing a clock signal to the circuits, the clock signal comprising the selected clock cycle for each circuit, and tuning the reset signal relative to the clock signal based on a center of the selected clock cycle for each circuit. The method also includes providing the reset signal to the circuits and asserting the reset signal in the circuits based on the mask. A system and a non-transitory, machine-readable medium storing instructions to perform the above method are also provided.

Abstract: A method implemented in a memory device, wherein the memory device comprises a first memory and a second memory, the method comprising receiving a direct memory access (DMA) write request from a first central processing unit (CPU) in a first computing system, wherein the DMA write request is for a plurality of bytes of data, in response to the DMA write request receiving the plurality of bytes of data from a memory in the first computing system without processing by the first CPU, and storing the plurality of bytes of data in the first memory, and upon completion of the storing, sending an interrupt message to a second CPU in a second computing system, wherein the interrupt message is configured to interrupt processing of the second CPU and initiate transfer of the plurality of bytes of data to a memory in the second computing system.

Abstract: A method implemented in a memory device, wherein the memory device comprises a first memory and a second memory, the method comprising receiving a direct memory access (DMA) write request from a first central processing unit (CPU) in a first computing system, wherein the DMA write request is for a plurality of bytes of data, in response to the DMA write request receiving the plurality of bytes of data from a memory in the first computing system without processing by the first CPU, and storing the plurality of bytes of data in the first memory, and upon completion of the storing, sending an interrupt message to a second CPU in a second computing system, wherein the interrupt message is configured to interrupt processing of the second CPU and initiate transfer of the plurality of bytes of data to a memory in the second computing system.

Abstract: A network element (NE) comprising a processor configured to receive a resource request via a Peripheral Component Interconnect (PCI) Express (PCI-e) network from a first device, wherein the first device is external to the NE, and query an access control list to determine whether the first device has permission to access a resource. The disclosure also includes an apparatus comprising a memory comprising instructions, and a processor configured to execute the instructions by allocating a resource of a shared device for use by an external device over a PCI-e network by updating a resource allocation table.

Abstract: A method and apparatus is provided for integrating a logic level simulation with an instruction level simulation for more accurate and faster system level simulation for testing. A host system or processors (CPU) is simulated by the instruction level simulator and the simulation of an input/output subsystem is modeled by the logic level simulator. The two simulations work side by side communicating through an interprocess communication (IPC) device and both simulations can perform a read/write access. Hence, a DMA and a slave access can occur at the same time causing a deadlock situation where both simulators are waiting for data and acknowledgment from each other at the same time. An input/output subsystem SBus module resolves this deadlock by deferring the non-DMA transaction. Finally, the synchronization of the two simulations is handled by the invention allowing the two simulators to run as asynchronous peers.