Abstract: An example apparatus described herein to implement cancellation pulse generation includes a first memory storing first subsets of data samples of a single pulse cancellation waveform. The example apparatus includes a second memory storing second subsets of data samples of the single pulse cancellation waveform, the second subsets including different data samples of the single pulse cancellation waveform than the first subsets. The example apparatus includes first circuitry coupled to the first memory and to the second memory in parallel. The example apparatus includes a plurality of buffers. The example apparatus includes second circuitry coupled to the plurality of buffers.

Abstract: An example apparatus includes: crest factor reduction circuitry having a signal input and a peak cancellation waveform input; and peak cancellation waveform generator circuitry including: carrier profile analyzer circuitry having a signal input coupled to the signal input of the crest factor reduction circuitry, and having a carrier profile output; waveform construction circuitry having a carrier profile input coupled to the carrier profile output of the carrier profile analyzer circuitry, having a second input, and having a peak cancellation waveform output coupled to the peak cancellation waveform input of the crest factor reduction circuitry; and profile change detector circuitry having a carrier profile input coupled to the carrier profile output of the carrier profile analyzer circuitry, and having an output coupled to the second input of the waveform construction circuitry.

Abstract: A TX-TX pre-compensation system that estimates unwanted coupling in a victim transmit chain caused by an aggressor transmit chain and injects a pre-compensation signal to cancel out the estimated coupling. In some embodiments, a signal measurement module estimates the amplitude, phase, and envelope delay of the coupling and an isolation pre-compensation module generates the pre-compensation signal based on the estimated amplitude, the estimated phase, the estimated envelope delay, and the difference between the carrier frequencies of the transmit chains. Since the phase of the coupling may be affected by the carrier frequency of the transmit chains, in some embodiments the phase of the pre-compensation signal is adjusted in response to a change in carrier frequency. Since the amplitude of the coupling may be affected by attenuator gain settings, in some embodiments the amplitude of the pre-compensation signal may be adjusted in response to a change in attenuator gain setting.

Abstract: A TX-TX pre-compensation system that estimates unwanted coupling in a victim transmit chain caused by an aggressor transmit chain and injects a pre-compensation signal to cancel out the estimated coupling. In some embodiments, a signal measurement module estimates the amplitude, phase, and envelope delay of the coupling and an isolation pre-compensation module generates the pre-compensation signal based on the estimated amplitude, the estimated phase, the estimated envelope delay, and the difference between the carrier frequencies of the transmit chains. Since the phase of the coupling may be affected by the carrier frequency of the transmit chains, in some embodiments the phase of the pre-compensation signal is adjusted in response to a change in carrier frequency. Since the amplitude of the coupling may be affected by attenuator gain settings, in some embodiments the amplitude of the pre-compensation signal may be adjusted in response to a change in attenuator gain setting.

Abstract: An integrated circuit comprises an input, a digital step attenuator, an analog-to-digital converter, a first output, a second output, a first bandwidth filter, a first band attack detector, a first band decay detector, a second bandwidth filter, a second band attack detector, a second band decay detector, and an automatic gain control. The ADC is configured to output a digital signal including a first and a second frequency range. The first and second bandwidth filters are configured to extract respective digital signals comprising the first and second frequency ranges. The band attack and decay detectors are configured to detect band peaks or decays thereof such that the DSA and External AMP may be controlled by means of the AGC based on the detected band peaks or decays, and ADC attack and ADC decay.

Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.

Abstract: An integrated circuit comprises an input, a digital step attenuator, an analog-to-digital converter, a first output, a second output, a first bandwidth filter, a first band attack detector, a first band decay detector, a second bandwidth filter, a second band attack detector, a second band decay detector, and an automatic gain control. The ADC is configured to output a digital signal including a first and a second frequency range. The first and second bandwidth filters are configured to extract respective digital signals comprising the first and second frequency ranges. The band attack and decay detectors are configured to detect band peaks or decays thereof such that the DSA and External AMP may be controlled by means of the AGC based on the detected band peaks or decays, and ADC attack and ADC decay.

Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.

Abstract: An IQ estimation module comprising a powerup state IQ estimator configured to generate powerup state IQ estimates based on a powerup calibration of the IQ estimation module, a steady state IQ estimator configured to generate steady state IQ estimates during a steady state operation of the IQ estimation module, and an IQ estimate extender configured to determine differences between the powerup state IQ estimates and steady state IQ estimates at their respective frequency bins and adjust the powerup state IQ estimates to improve the accuracy of IQ estimates.

Abstract: An IQ estimation module comprising a powerup state IQ estimator configured to generate powerup state IQ estimates based on a powerup calibration of the IQ estimation module, a steady state IQ estimator configured to generate steady state IQ estimates during a steady state operation of the IQ estimation module, and an IQ estimate extender configured to determine differences between the powerup state IQ estimates and steady state IQ estimates at their respective frequency bins and adjust the powerup state IQ estimates to improve the accuracy of IQ estimates.