Abstract: A multicore computing device includes a memory and a processor coupled to the memory. The processor includes plural cores and a multiple input multiple output (MIMO) block coupled to the cores. The MIMO block receives a halt request from a first core of the cores, transmits a core-halt request to one or more other cores other than the first core, to halt execution of the one or more other cores, and permits the first core to lock with a shared resource.

Abstract: The various embodiments of the present invention disclose a method for reducing interrupt latency in embedded systems. According to at least one example embodiment of the inventive concepts, the method for reducing interrupt latency in embedded systems, the method comprises steps of toggling, by a processor, from a supervisor (SVC) mode to an interrupt request (IRQ) mode on receiving an interrupt, identifying, by the processor, a Task Control Block (TCB) of a preempted task on receiving the interrupt, enabling, by the processor, the IRQ stack as a pseudo preempted task context table, and storing the preempted task context information in the IRQ stack, wherein a register set is stored in IRQ stack before processing the received interrupt.

Abstract: A method and system for providing memory management in a Real-Time Operating System (RTOS) based system are provided. The method includes creating a plurality of tasks with a two level stack scheme comprising a first level stack and a second level stack, scheduling a first task for execution by moving a stack pointer from the first level stack to the second level stack, determining whether the first task is pre-empted, allocating the second level stack to the first task in a second state if the first task is not pre-empted, changing an active task for execution, determining whether the first task relinquishes control from the second state and is waiting for a resource, moving the stack pointer back from the second level stack to the first level stack if the first task relinquishes itself and providing the second level stack for use by a second task.

Abstract: The various embodiments of the present invention disclose a method for reducing interrupt latency in embedded systems. According to at least one example embodiment of the inventive concepts, the method for reducing interrupt latency in embedded systems, the method comprises steps of toggling, by a processor, from a supervisor (SVC) mode to an interrupt request (IRQ) mode on receiving an interrupt, identifying, by the processor, a Task Control Block (TCB) of a preempted task on receiving the interrupt, enabling, by the processor, the IRQ stack as a pseudo preempted task context table, and storing the preempted task context information in the IRQ stack, wherein a register set is stored in IRQ stack before processing the received interrupt.

Abstract: A method for group-based scheduling in a multi-core processor apparatus comprises computing a cost of at least two tasks accessing a same resource based on a plurality of parameters; determining, by the multi-core processor apparatus, inter-dependent tasks from among a plurality of tasks based on a plurality of parameters by comparing the computed cost of the at least two tasks with a task inter-dependent threshold; generating, by the multi-core processor apparatus, at least one task group including the inter-dependent tasks; and scheduling, by multi-core processor apparatus, at least one inter-dependent task from the at least one task group on a core of the multi-core processor apparatus.

Abstract: A method of Physical Multicast Channel (PMCH) decoding for Multicast Broadcast Single Frequency Network (MBSFN) by a UE includes decoding a Transport Block (TB) in a first sub-frame of a Multicast Channel Scheduling Period (MSP) by a Physical (PHY) layer in the UE; providing the decoded TB to a Media Access Control (MAC) layer; performing blind decoding on all received MBSFN sub-frames, until the PHY layer receives PMCH scheduling configuration from the MAC layer; selecting at least one Logical Channel IDentifier (LCID) and Multicast Transport Channel (MTCH) scheduling information for each LCID by decoding a Multicast Channel Scheduling Information Protocol Data Unit (MSI PDU), the MSI PDU present in the decoded TB; building a PMCH scheduling configuration by the MAC layer based on the selected at least one LCID and the MTCH scheduling information; passing the PMCH scheduling configuration to the PHY layer by the MAC layer; and applying the PMCH scheduling configuration.

Abstract: An apparatus and method are provided for interrupt handling. A method includes receiving, by an accelerator unit, an interrupt request; stacking, by the accelerator unit, a plurality of general purpose registers in an inbuilt last in first out (LIFO) unit; and sending, by the accelerator unit, a vector address corresponding to the interrupt request to a processor, which processes the interrupt request.

Abstract: A method and system for providing memory management in a Real-Time Operating System (RTOS) based system are provided. The method includes creating a plurality of tasks with a two level stack scheme comprising a first level stack and a second level stack, scheduling a first task for execution by moving a stack pointer from the first level stack to the second level stack, determining whether the first task is pre-empted, allocating the second level stack to the first task in a second state if the first task is not pre-empted, changing an active task for execution, determining whether the first task relinquishes control from the second state and is waiting for a resource, moving the stack pointer back from the second level stack to the first level stack if the first task relinquishes itself and providing the second level stack for use by a second task.

Abstract: Method and apparatuses are provided for providing preemptive task scheduling for a Real Time Operating System (RTOS). A two-level priority is assigned to each task that is created. The two-level priority includes a kernel priority and a user-defined priority. A priority bitmap corresponding to the kernel priority is created. A priority bit in the priority bitmap is enabled. The priority bit indicates a status of a respective task.

Abstract: A method and system for providing memory management in a Real-Time Operating System (RTOS) based system are provided. The method includes creating a plurality of tasks with a two level stack scheme comprising a first level stack and a second level stack, scheduling a first task for execution by moving a stack pointer from the first level stack to the second level stack, determining whether the first task is pre-empted, allocating the second level stack to the first task in a second state if the first task is not pre-empted, changing an active task for execution, determining whether the first task relinquishes control from the second state and is waiting for a resource, moving the stack pointer back from the second level stack to the first level stack if the first task relinquishes itself and providing the second level stack for use by a second task.

Abstract: A method of Physical Multicast Channel (PMCH) decoding for Multicast Broadcast Single Frequency Network (MBSFN) by a UE includes decoding a Transport Block (TB) in a first sub-frame of a Multicast Channel Scheduling Period (MSP) by a Physical (PHY) layer in the UE; providing the decoded TB to a Media Access Control (MAC) layer; performing blind decoding on all received MBSFN sub-frames, until the PHY layer receives PMCH scheduling configuration from the MAC layer; selecting at least one Logical Channel IDentifier (LCID) and Multicast Transport Channel (MTCH) scheduling information for each LCID by decoding a Multicast Channel Scheduling Information Protocol Data Unit (MSI PDU), the MSI PDU present in the decoded TB; building a PMCH scheduling configuration by the MAC layer based on the selected at least one LCID and the MTCH scheduling information; passing the PMCH scheduling configuration to the PHY layer by the MAC layer; and applying the PMCH scheduling configuration.

Abstract: Method and apparatuses are provided for providing preemptive task scheduling for a Real Time Operating System (RTOS). A two-level priority is assigned to each task that is created. The two-level priority includes a kernel priority and a user-defined priority. A priority bitmap corresponding to the kernel priority is created. A priority bit in the priority bitmap is enabled.

Abstract: A method and system for providing power management in a system employing a Central Processing Unit (CPU) and an operating system are provided. The method includes monitoring idle times of the CPU; predicting an idle pattern based on the monitored idle times; and determining a selective sleep of a peripheral device based on the predicted CPU idle pattern.

Abstract: A method and system for providing memory management in a Real-Time Operating System (RTOS) based system are provided. The method includes creating a plurality of tasks with a two level stack scheme comprising a first level stack and a second level stack, scheduling a first task for execution by moving a stack pointer from the first level stack to the second level stack, determining whether the first task is pre-empted, allocating the second level stack to the first task in a second state if the first task is not pre-empted, changing an active task for execution, determining whether the first task relinquishes control from the second state and is waiting for a resource, moving the stack pointer back from the second level stack to the first level stack if the first task relinquishes itself and providing the second level stack for use by a second task.