Abstract: A processor includes a plurality of cores configured to perform operations independently, a memory, and a control circuit electrically connected to the plurality of cores and the memory. The control circuit is configured to acquire one or more instructions associated with a task, store data corresponding to the task based on the one or more instructions, transmit the instructions to the at least some cores, check one or more cores that have responded to the instructions among the at least some cores, prevent the task from being allocated to the cores except for one core if the task is allocated to the one core, and allocate the task to one of the cores, the allocation of the task including changing state information associated with the allocation and setting other cores not allocated the task among the plurality of cores not to access the data corresponding to the task.

Abstract: An electronic device may comprise: a first memory for storing first data at a designated rate; a first processor connected to the first memory and configured to divide the first data into multiple second data, each having a size smaller than the size of the first data; a second memory for storing at least some of the multiple second data at a rate faster than the designated rate; a second processor connected to the second memory and configured to process the at least some of the multiple second data; and a DMA control module, connected to the second processor, for transmitting/receiving data between the first memory and the second memory, wherein the DMA control module is configured to: at least on the basis of a processing command for the multiple second data which is transmitted from the first processor to the second processor, receive, from the first memory, the at least some of the multiple small-sized second data divided from the first data; transmit the at least some of the multiple second data to the s

Abstract: An electronic device may comprise: a first memory for storing first data at a designated rate; a first processor connected to the first memory and configured to divide the first data into multiple second data, each having a size smaller than the size of the first data; a second memory for storing at least some of the multiple second data at a rate faster than the designated rate; a second processor connected to the second memory and configured to process the at least some of the multiple second data; and a DMA control module, connected to the second processor, for transmitting/receiving data between the first memory and the second memory, wherein the DMA control module is configured to: at least on the basis of a processing command for the multiple second data which is transmitted from the first processor to the second processor, receive, from the first memory, the at least some of the multiple small-sized second data divided from the first data; transmit the at least some of the multiple second data to the s

Abstract: The present disclosure relates to system resource management in a variety of situations. The present disclosure provides a method and an apparatus for reducing memory requirements and improving processing speed when an electronic device performs padding for a particular arithmetic operation on data. To achieve the above objective, a method for operating an electronic device according to the present disclosure comprises the steps of: reading a first portion of data from a first memory; determining a first padding address based on the address of a byte belonging to a boundary region of the data among a plurality of bytes included in the first portion; writing values of the plurality of bytes and a value corresponding to the first padding address to a second memory; and reading a second portion of the data from the first memory.

Abstract: Provided are a method of processing images and an electronic device thereof. The electronic device includes a memory and a processor operatively connected to the memory. The processor is configured to divide an image into a plurality of sub images, load information about a first sub image of the plurality of sub images into the memory, perform image processing on the first sub image, load information about an image area that does not overlap with the first sub image of a second sub image located in a longitudinal direction of the first sub image into the memory, and perform image processing on the second sub image.

Abstract: A processor includes a plurality of cores configured to perform operations independently, a memory, and a control circuit electrically connected to the plurality of cores and the memory. The control circuit is configured to acquire one or more instructions associated with a task, store data corresponding to the task based on the one or more instructions, transmit the instructions to the at least some cores, check one or more cores that have responded to the instructions among the at least some cores, prevent the task from being allocated to the cores except for one core if the task is allocated to the one core, and allocate the task to one of the cores, the allocation of the task including changing state information associated with the allocation and setting other cores not allocated the task among the plurality of cores not to access the data corresponding to the task.

Abstract: A method and an apparatus for performing task scheduling in a terminal are provided. The terminal includes at least two different types of cores and determines if a change in a task state has occurred in response to at least one of the two cores, If a change in a task state has occurred, the terminal determines, for said at least one core, the variation in the duration of each of a plurality of tasks being executed, predicts the duration of each of the plurality of tasks on the basis of the change in the task state using the determined variation, and performs task scheduling for said at least one core in accordance with the predicted duration.

Abstract: The present disclosure relates to system resource management in a variety of situations. The present disclosure provides a method and an apparatus for reducing memory requirements and improving processing speed when an electronic device performs padding for a particular arithmetic operation on data. To achieve the above objective, a method for operating an electronic device according to the present disclosure comprises the steps of: reading a first portion of data from a first memory; determining a first padding address based on the address of a byte belonging to a boundary region of the data among a plurality of bytes included in the first portion; writing values of the plurality of bytes and a value corresponding to the first padding address to a second memory; and reading a second portion of the data from the first memory.

Abstract: A method for controlling performance of an electronic device is provided. The method includes sensing user input, predicting user input speed, and controlling at least one processing unit of the electronic device based on a predicted user input speed and performance assignment information. Here, the performance assignment information includes control information mapped respectively with user input speeds for controlling the at least one processing unit of the electronic device.

Abstract: An apparatus includes a calculation processing unit configured to perform a calculation in the electronic device, a device manager configured to controls a speed of the calculation processing unit and output load factor information, one or more user-level application programs with a respective load factor limit, configured to request for load factor limit information of the calculation processing unit and calculation of a load with a load factor limit, and a service quality manager configured to receive the load factor limit information and the load with the load factor limit from the user-level application programs with the load factor limit, receive load factor information of the calculation processing unit from the device manager, generate a calculation parameter so that a load factor of the calculation processing unit is within the load factor limit information, and output the load with the load factor limit and the generated calculation parameter.

Abstract: A method for controlling performance of an electronic device is provided. The method includes sensing user input, predicting user input speed, and controlling at least one processing unit of the electronic device based on a predicted user input speed and performance assignment information. Here, the performance assignment information includes control information mapped respectively with user input speeds for controlling the at least one processing unit of the electronic device.

Abstract: An apparatus includes a calculation processing unit configured to perform a calculation in the electronic device, a device manager configured to controls a speed of the calculation processing unit and output load factor information, one or more user-level application programs with a respective load factor limit, configured to request for load factor limit information of the calculation processing unit and calculation of a load with a load factor limit, and a service quality manager configured to receive the load factor limit information and the load with the load factor limit from the user-level application programs with the load factor limit, receive load factor information of the calculation processing unit from the device manager, generate a calculation parameter so that a load factor of the calculation processing unit is within the load factor limit information, and output the load with the load factor limit and the generated calculation parameter.

Abstract: An apparatus and method for photographing a subject in a photographing device are provided. The method includes determining a capture pose; determining a pose of a subject for photographing; and photographing the subject automatically based on a similarity between the capture pose and the pose of the subject.

Abstract: A method and an apparatus for performing task scheduling in a terminal are provided. The terminal includes at least two different types of cores and determines if a change in a task state has occurred in response to at least one of the two cores, If a change in a task state has occurred, the terminal determines, for said at least one core, the variation in the duration of each of a plurality of tasks being executed, predicts the duration of each of the plurality of tasks on the basis of the change in the task state using the determined variation, and performs task scheduling for said at least one core in accordance with the predicted duration.

Abstract: A method and apparatus for booting an electronic device are provided. The method includes collecting context information regarding the electronic device; determining whether a use of the electronic device is expected based on the collected context information; and when the use of the electronic device is expected, supplying electric power to at least one of predetermined elements of the electronic device.

Abstract: An apparatus and method for photographing a subject in a photographing device are provided. The method includes determining a capture pose; determining a pose of a subject for photographing; and photographing the subject automatically based on a similarity between the capture pose and the pose of the subject.