Abstract: A method of improved simulator processing is provided. The method according to the current invention includes grouping frequently accessed data into one set id to improve memory hierarchy performance. The method further includes simulating predication in a non-predicated architecture to improve CPU performance. The simulated predication includes pseudo-predicated implementation of read-operation vector element access pseudo-predicated implementation of write-operation vector element access, and predicated implementation of multi-way branches with assignment statements having a same left-hand-side (lhs). The method further includes determining a selection path in a multi-sensitive “always” block to reduce taken branches. The multi-sensitive “always” block selection path determination includes generating instance-specific code to save port allocation storage, and generating inlined instance-specific code to combine sensitive actions.

Abstract: A microprocessor includes an MMU which converts from a virtual address to a physical address, and an LSU which controls an execution of a load/store instruction. The LSU includes a DCACHE which temporarily stores data to read out from and to write into an external memory, an SPRAM used for a specific purpose besides caching, and an address generator which generates the virtual address to access the DCACHE and the SPRAM. The MMU generates a conversion table which performs a conversion from the virtual address to the physical address. A flag information showing whether or not the access to the SPRAM is performed is included in this conversion table. The LSU absolutely accesses the SPRAM if the flag is being set. Accordingly, it is unnecessary to allocate the SPRAM to a memory map of the main memory, and the allocation of the memory map simplifies.

Abstract: A processor includes n-bit (e.g., 128-bit) register circuitry for holding instruction operands. Instruction decode circuitry decodes processor instructions from an instruction stream. Arithmetic logic (AL) circuitry is operable to perform one of a single operation on at least one m-bit maximum (e.g., 64-bit) operand provided from the n-bit register circuitry, responsive to a first single processor instruction decoded by the instruction decode circuitry, wherein m<n. In addition, the AL circuitry is operable to perform multiple parallel operations on at least two portions of one n-bit operand provided from the n-bit register circuitry. The multiple parallel operations are performed responsive to a second single instruction decoded by the instruction decode circuitry.