Patents by Inventor Rakesh Dodeja

Rakesh Dodeja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9825952
    Abstract: An embodiment of the invention allows a network access server to control network access for individual applications that run on a device. The device may be included in a machine-to-machine environment. The embodiment may provide a secure channel between the network access server and the device access layer and another secure channel between the device access layer and the device application layer. Thus, before applications are allowed to access the network those applications may be required to authenticate themselves via a secure channel. Other embodiments are described herein.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Ashok Sunder Rajan, Rakesh Dodeja, David A. De Vries, Hemaprabhu Jayanna, William J. Tiso, Kevin W. Bross, Robert J. Hunter
  • Patent number: 9104409
    Abstract: A method to reduce memory power consumption for a computing platform includes inspecting an operating parameter associated with a resource of the computing platform that is updated by the resource of the computing platform during runtime of the computing platform. Memory power utilization is then predicted for the computing platform during the runtime of the computing platform based at least in part on the operating parameter. A current power state of at least one memory module resident on the computing platform is transitioned to one of a plurality of power states based on the predicting of the memory power utilization.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: August 11, 2015
    Assignee: Intel Corporation
    Inventors: Rakesh Dodeja, Neelam Chandwani, Chetan Hiremath, Udayan Mukherjee, Anthony Ambrose
  • Patent number: 8868034
    Abstract: Embodiments may comprise logic such as hardware and/or code to provide a secure device area network. Many embodiments comprise a gateway node or enterprise enhanced node with a services distribution frame installed on a customer's premises. The gateway node or enterprise enhanced node may interconnect the secure wireless device area network at the customer's premises with a cellular network. In many embodiments, the cellular network core may provision authentication credentials and security keys, and manage access polies to facilitate access by Application Service Providers to devices on premises including smart devices via a security and policy enforcement function of a services distribution frame of the gateway node or enterprise enhanced node, Authorized members of the secure wireless device area network may connect to the Wide Area Network (WAN) through the gateway node and the cellular network core.
    Type: Grant
    Filed: December 25, 2010
    Date of Patent: October 21, 2014
    Assignee: Intel Corporation
    Inventors: Rakesh Dodeja, Ashok Sunder Rajan, Kevin D. Johnson, Martin Mcdonnell, William J. Tiso, Todd A. Keaffaber, Adam P. Burns
  • Publication number: 20140143833
    Abstract: An embodiment of the invention allows a network access server to control network access for individual applications that run on a device. The device may be included in a machine-to-machine environment. The embodiment may provide a secure channel between the network access server and the device access layer and another secure channel between the device access layer and the device application layer. Thus, before applications are allowed to access the network those applications may be required to authenticate themselves via a secure channel. Other embodiments are described herein.
    Type: Application
    Filed: December 30, 2011
    Publication date: May 22, 2014
    Inventors: Ashok Sunder Rajan, Rakesh Dodeja, David A. De Vries, Hemprabhu Jayanna, William J. Tiso, Kevin W. Bross, Robert J. Hunter
  • Publication number: 20140122897
    Abstract: Integrity management architecture is extended with trusted hash provisioning. The trusted hash provisioning ensures the integrity of a computing device. Thus, a multipurpose device can be as secure as a dedicated single-purpose device. The trusted hash provisioning includes determining a hash mask, and computing a trusted hash computation based on signatures of components identified as included within the scope of the hash. The computed trusted hash computation is used to determine integrity of the computing device.
    Type: Application
    Filed: December 31, 2011
    Publication date: May 1, 2014
    Inventors: Rakesh Dodeja, Alex De Vries, Ashok Sunder Rajan, Hemaprabhu Jayanna, William J. Tiso, Kevin W. Bross, Robert Hunter
  • Patent number: 8412972
    Abstract: Described herein are a method and an apparatus for reducing power consumption of memories by monitoring the power states of the memories via an operating system. The method comprises reading counter values corresponding to power states of each memory of a plurality memories; computing a power state usage corresponding to the power states of each memory of the plurality, the computing based on the counter values; determining whether the power state usage exceeds a predetermined threshold usage; and adjusting current and future usage of each memory of the plurality in response to determining that the power state usage exceeds the predetermined threshold usage.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: April 2, 2013
    Assignee: Intel Corporation
    Inventors: Kin-Hang Cheung, Neelam Chandwani, Chetan D. Hiremath, Udayan Mukherjee, Rakesh Dodeja
  • Publication number: 20120164975
    Abstract: Embodiments may comprise logic such as hardware and/or code to provide a secure device area network. Many embodiments comprise a gateway node or enterprise enhanced node with a services distribution frame installed on a customer's premises. The gateway node or enterprise enhanced node may interconnect the secure wireless device area network at the customer's premises with a cellular network. In many embodiments, the cellular network core may provision authentication credentials and security keys, and manage access polies to facilitate access by Application Service Providers to devices on premises including smart devices via a security and policy enforcement function of a services distribution frame of the gateway node or enterprise enhanced node, Authorized members of the secure wireless device area network may connect to the Wide Area Network (WAN) through the gateway node and the cellular network core.
    Type: Application
    Filed: December 25, 2010
    Publication date: June 28, 2012
    Inventors: Rakesh Dodeja, Ashok Sunder Rajan, Kevin D. Johnson, Martin Mcdonnell, William J. Tiso, Todd A. Keaffaber, Adam P. Burns
  • Publication number: 20110320847
    Abstract: Described herein are a method and an apparatus for reducing power consumption of memories by monitoring the power states of the memories via an operating system. The method comprises reading counter values corresponding to power states of each memory of a plurality memories; computing a power state usage corresponding to the power states of each memory of the plurality, the computing based on the counter values; determining whether the power state usage exceeds a predetermined threshold usage; and adjusting current and future usage of each memory of the plurality in response to determining that the power state usage exceeds the predetermined threshold usage.
    Type: Application
    Filed: June 28, 2010
    Publication date: December 29, 2011
    Inventors: Kin-Hang Cheung, Neelam Chandwani, Chetan D. Hiremath, Udayan Mukherjee, Rakesh Dodeja
  • Patent number: 8024594
    Abstract: Disclosed is a method, apparatus and computer program product for reducing memory power consumption in a server system. The server system includes a memory controller and a plurality of Dual Inline Memory Modules (DIMMs). The method for reducing the memory power consumption includes determining a status of a channel of a plurality of channels of the memory controller. The plurality of channels is associated with the plurality of DIMMs of the server system. The status of the channel represents a presence of at least one scheduled transaction in the channel. The method further includes monitoring the status of the channel by checking whether the status of the channel is in an idle mode for a period of at least equal to a first threshold time. Thereafter, the method includes driving the channel into a power down state based on the monitoring of the status of the channel.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: September 20, 2011
    Assignee: Intel Corporation
    Inventors: Yean Kee Yong, Durgesh Srivastava, Niall D. McDonnell, Rakesh Dodeja, Neelam Chandwani
  • Publication number: 20100191997
    Abstract: A method is to include implementing at least one statistical prediction model to predict memory power utilization and reduce power consumption for a computing platform. The implementation includes determining a configuration parameter for the computing platform, monitoring an operating parameter for the computing platform and predicting memory power utilization for the computing platform based on the determined configuration parameter and the monitored operating parameter. The method is to also include transitioning at least one memory module resident on the computing platform to one of a plurality of power states based at least in part on memory power utilization predicted via the implementation of the at least one statistical prediction model.
    Type: Application
    Filed: April 1, 2010
    Publication date: July 29, 2010
    Applicant: INTEL CORPORATION
    Inventors: Rakesh Dodeja, Neelam Chandwani, Chetan Hiremath, Udayan Mukherjee, Anthony Ambrose
  • Patent number: 7752468
    Abstract: A method is to include implementing at least one statistical prediction model to predict memory power utilization and reduce power consumption for a computing platform. The implementation includes determining a configuration parameter for the computing platform, monitoring an operating parameter for the computing platform and predicting memory power utilization for the computing platform based on the determined configuration parameter and the monitored operating parameter. The method is to also include transitioning at least one memory module resident on the computing platform to one of a plurality of power states based at least in part on memory power utilization predicted via the implementation of the at least one statistical prediction model.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: July 6, 2010
    Assignee: Intel Corporation
    Inventors: Rakesh Dodeja, Neelam Chandwani, Chetan Hiremath, Udayan Mukherjee, Anthony Ambrose
  • Patent number: 7702966
    Abstract: A method for managing a system includes monitoring a plurality of applications running in the system for errors. A prediction is made as to whether errors detected would result in a failure. Fault recovery is initiated in response to a failure prediction. According to one aspect of the present invention, monitoring the plurality of applications includes reading error recorders associated with error occurrence. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Neelam Chandwani, Udayan Mukherjee, Chetan Hiremath, Rakesh Dodeja
  • Publication number: 20090249102
    Abstract: Disclosed is a method, apparatus and computer program product for reducing memory power consumption in a server system. The server system includes a memory controller and a plurality of Dual Inline Memory Modules (DIMMs). The method for reducing the memory power consumption includes determining a status of a channel of a plurality of channels of the memory controller. The plurality of channels is associated with the plurality of DIMMs of the server system. The status of the channel represents a presence of at least one scheduled transaction in the channel. The method further includes monitoring the status of the channel by checking whether the status of the channel is in an idle mode for a period of at least equal to a first threshold time. Thereafter, the method includes driving the channel into a power down state based on the monitoring of the status of the channel.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Applicant: INTEL CORPORATION
    Inventors: Yean Kee Yong, Durgesh Srivastava, Niall D. McDonnell, Rakesh Dodeja, Neelam Chandwani
  • Patent number: 7558849
    Abstract: A hardware management module is enabled to perform hardware management for a modular platform system that includes a plurality of modular platform shelves coupled via one or more communication links in a network. Hardware management to include monitoring board interfaces resident on one or more backplanes within the plurality of modular platform shelves, detecting when a board is received and coupled to a board interface and performing one or more hardware management functions to include obtaining field replaceable unit information from the detected board.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: July 7, 2009
    Assignee: Intel Corporation
    Inventors: Neelam Chandwani, Udayan Mukherjee, Chetan Hiremath, Rakesh Dodeja
  • Patent number: 7424396
    Abstract: Faults are monitored with information from agents for a plurality of sensors located on a plurality of circuit boards. A policy containing a error event thresholds against which the stored sensor information can be compared. Actions can be initiated by a fault module when one or more of the error event thresholds is exceeded.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Rakesh Dodeja, Neelam Chandwani, Chetan Hiremath, Wen Wei, Udayan Mukherjee
  • Patent number: 7424666
    Abstract: A fault module supports detection, analysis, and/or logging of various faults in a processor system. In one embodiment, the system is provided on a multi-core, single die device.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Neelam Chandwani, Udayan Mukheriee, Santosh Balakrishnan, Rakesh Dodeja, Chetan Hiremath
  • Publication number: 20070283178
    Abstract: A method is to include implementing at least one statistical prediction model to predict memory power utilization and reduce power consumption for a computing platform. The implementation includes determining a configuration parameter for the computing platform, monitoring an operating parameter for the computing platform and predicting memory power utilization for the computing platform based on the determined configuration parameter and the monitored operating parameter. The method is to also include transitioning at least one memory module resident on the computing platform to one of a plurality of power states based at least in part on memory power utilization predicted via the implementation of the at least one statistical prediction model.
    Type: Application
    Filed: June 6, 2006
    Publication date: December 6, 2007
    Inventors: Rakesh Dodeja, Neelam Chandwani, Chetan Hiremath, Udayan Mukherjee, Anthony Ambrose
  • Patent number: 7283921
    Abstract: A modeling module is disclosed that couples to a modular platform chassis. The modeling module includes a resident management controller to implement a test to model a component layout for a module to be received and coupled to the modular platform chassis. The test includes an operating thermal load for a component resident on the module at a given location. The module has a dimensional length and width that is similar to that of the modeling module. The modeling module also includes a thermal load device that is responsive to the management controller. The thermal load device is to implement at least a portion of the test by simulating the operating thermal load for the component resident on the module at the given location.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: October 16, 2007
    Assignee: Intel Corporation
    Inventors: Neelam Chandwani, Udayan Mukherjee, Wen Wei, Chetan Hiremath, Rakesh Dodeja, Kevin W. Bross
  • Publication number: 20070089011
    Abstract: Faults are monitored with information from agents for a plurality of sensors located on a plurality of circuit boards. A policy containing a error event thresholds against which the stored sensor information can be compared. Actions can be initiated by a fault module when one or more of the error event thresholds is exceeded.
    Type: Application
    Filed: September 26, 2005
    Publication date: April 19, 2007
    Inventors: Rakesh Dodeja, Neelam Chandwani, Chetan Hiremath, Wen Wei, Udayan Mukherjee
  • Publication number: 20070055914
    Abstract: A method for managing a system includes monitoring a plurality of applications running in the system for errors. A prediction is made as to whether errors detected would result in a failure. Fault recovery is initiated in response to a failure prediction. According to one aspect of the present invention, monitoring the plurality of applications includes reading error recorders associated with error occurrence. Other embodiments are described and claimed.
    Type: Application
    Filed: September 7, 2005
    Publication date: March 8, 2007
    Inventors: Neelam Chandwani, Udayan Mukherjee, Chetan Hiremath, Rakesh Dodeja