Patents by Inventor Rakesh H. Patel
Rakesh H. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6285211Abstract: An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (“FPGA”), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a FPGA core. Each input/output buffer circuit allows at least two signals to be time-multiplexed onto an input/output pin thereby doubling the effective input/output capacity. The input/output buffer circuits may be used to time-multiplex at least two signals onto an input pin, at least two signals onto an output pin, or both. Each input/output buffer circuit further has shared flip flops for time-multiplexing signals. The circuitry provides two connections into the FPGA core which can be used to time-multiplex at least two independent inputs or outputs.Type: GrantFiled: December 13, 1999Date of Patent: September 4, 2001Assignees: Altera Corporation, Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Michael R. Butts, Kevin A. Norman, Rakesh H. Patel
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Patent number: 6259588Abstract: An overcurrent protection circuit for input/Output (I/O) buffers for a Field Programmable Gate Array wherein short circuits can be detected and the output current limited so as to avoid damaging the device. I/O buffers having the overcurrent protection circuit can detect a contention between the buffers. In order to eliminate the contention, certain I/O buffers will go into a noncontending state.Type: GrantFiled: December 29, 1999Date of Patent: July 10, 2001Assignees: Altera Corporation, Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Michael R. Butts, Kevin A. Norman, Rakesh H. Patel
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Patent number: 6252422Abstract: An input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an “overvoltage condition.” For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator (1002) for preventing leakage current paths.Type: GrantFiled: September 22, 1999Date of Patent: June 26, 2001Assignee: Altera CorporationInventors: Rakesh H. Patel, John E. Turner, Wilson Wong
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Patent number: 6243304Abstract: A programmable logic device (PLD) that provides the capability to observe and control the logic state of buried internal nodes is disclosed. The PLD provides shadow storage units for internal nodes such as logic element registers, memory cells, and I/O registers. A sample/load data path includes bidirectional data buses and shift register that facilitate the sampling of internal nodes for observing their logic states, and loading of internal nodes for controlling their logic states.Type: GrantFiled: November 12, 1999Date of Patent: June 5, 2001Assignee: Altera CorporationInventors: Rakesh H. Patel, Kevin A. Norman
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Patent number: 6219284Abstract: An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (“FPGA”), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.Type: GrantFiled: September 24, 1999Date of Patent: April 17, 2001Assignees: Altera Corporation, Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Michael R. Butts, Kevin A. Norman, Rakesh H. Patel, Chao Chiang Chen
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Look-up table based logic element with complete permutability of the inputs to the secondary signals
Patent number: 6184707Abstract: A logic element for a programmable logic device. The logic element includes a look-up table (400) for implementing logical functions, a programmable delay block (415), a storage block (430) configurable as a latch or a flip-flop, and a diagnostic shadow latch (435). A plurality of inputs (410) to the logic element and complements of these inputs are available to control the secondary functions of the storage block (430).Type: GrantFiled: October 7, 1998Date of Patent: February 6, 2001Assignees: Altera Corporation, Quickturn Design Systems, Inc.Inventors: Kevin A. Norman, Rakesh H. Patel, Stephen P. Sample, Michael R. Butts -
Patent number: 6175952Abstract: A technique of fabricating an integrated circuit adaptable for use in various operating voltage environments. The same integrated circuit design may be used in different operating modes depending on the particular option selected. For example, there may be three options (710, 715, 720). The various options of the integrated circuit formed on the same integrated circuit. During the fabrication of the integrated circuit, the desired option is selected. This may be accomplished, for example, by selecting the appropriate metal masks (725). Other techniques include, to name a few, using programmable links, programmable fuses, programmable cells, and many others. The technique of the present invention reduces the costs of integrated circuits. The same design may be used for a variety of purposes and in a variety of voltage environments without needing to develop and design a specific integrated circuit for each voltage condition.Type: GrantFiled: May 27, 1997Date of Patent: January 16, 2001Assignee: Altera CorporationInventors: Rakesh H. Patel, John E. Turner
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Patent number: 6151258Abstract: An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.Type: GrantFiled: October 27, 1999Date of Patent: November 21, 2000Assignees: Quickturn Design Systems, Inc., Altera CorporationInventors: Stephen P. Sample, Michael R. Butts, Kevin A. Norman, Rakesh H. Patel, Chao Chiang Chen
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Patent number: 6147511Abstract: An input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an "overvoltage condition. " For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator (1002) for preventing leakage current paths.Type: GrantFiled: May 27, 1997Date of Patent: November 14, 2000Assignee: Altera CorporationInventors: Rakesh H. Patel, John E. Turner, Wilson Wong
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Patent number: 6122209Abstract: A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.Type: GrantFiled: July 8, 1999Date of Patent: September 19, 2000Assignee: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
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Patent number: 6118302Abstract: A technique and circuitry to interface an integrated circuit to other circuits in a mixed-voltage mode environment. The integrated circuit operates at an internal supply voltage level. Externally, the integrated circuit will interface with an external supply voltage level, above the internal supply voltage level. The output signals from the integrated circuit will be compatible with the external supply level. Specifically, a level shifter (1317) or similar conversion circuit is used to convert voltages compatible with the internal supply level to be compatible with the external supply level.Type: GrantFiled: May 27, 1997Date of Patent: September 12, 2000Assignee: Altera CorporationInventors: John E. Turner, Rakesh H. Patel
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Patent number: 6107854Abstract: A speed path circuit includes a reference circuit and adjustable drive components that can be turned on or off to vary the speed path in order to meet minimum delay specification for the circuit. In an embodiment, one or more differential amplifiers are used to detect the strength of example circuit elements and generate a reference signal. An optional embodiment includes a mechanism for disconnecting the reference circuit to avoid any DC current drain. The invention may be used in a wide range of integrated circuits and may also be used in a programmable logic device (PLD). Reference circuits may be disconnected from a power source by using programmable logic elements.Type: GrantFiled: April 17, 1998Date of Patent: August 22, 2000Assignee: Altera CorporationInventors: Wilson Wong, John E. Turner, Thomas H. White, Rakesh H Patel
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Patent number: 6034857Abstract: An overcurrent protection circuit for input/Output (I/O) buffers for a Field Programmable Gate Array wherein short circuits can be detected and the output current limited so as to avoid damaging the device. I/O buffers having the overcurrent protection circuit can detect a contention between the buffers. In order to eliminate the contention, certain I/O buffers will go into a noncontending state.Type: GrantFiled: July 16, 1997Date of Patent: March 7, 2000Assignees: Altera Corporation, Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Michael R. Butts, Kevin A. Norman, Rakesh H. Patel
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Patent number: 6025737Abstract: A technique and circuitry for interfacing an integrated circuit manufactured using technology compatible with one voltage level to other integrated circuits compatible with a different voltage level. In particular, the integrated circuit is fabricated using technology compatible with an internal supply voltage level. Externally, the integrated circuit will interface with an external supply voltage level, above the internal supply voltage. The input and output signals to and from the integrated circuit will be compatible with the external supply level. The integrated circuit may include a voltage down converter (1330) and level shifter (1317).Type: GrantFiled: May 27, 1997Date of Patent: February 15, 2000Assignee: Altera CorporationInventors: Rakesh H. Patel, John E. Turner, John D. Lam, Wilson Wong
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Patent number: 6020760Abstract: An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a FPGA core. Each input/output buffer circuit allows at least two signals to be time-multiplexed onto an input/output pin thereby doubling the effective input/output capacity. The input/output buffer circuits may be used to time-multiplex at least two signals onto an input pin, at least two signals onto an output pin, or both. Each input/output buffer circuit further has shared flip flops for time-multiplexing signals. The circuitry provides two connections into the FPGA core which can be used to time-multiplex at least two independent inputs or outputs.Type: GrantFiled: July 16, 1997Date of Patent: February 1, 2000Assignees: Altera Corporation, Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Michael R. Butts, Kevin A. Norman, Rakesh H. Patel
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Patent number: 6020758Abstract: Various embodiments of a programmable logic device (PLD) capable of being dynamically partially reconfigured are disclosed. The PLD provides circuitry for changing its configuration data in whole or in part without halting the operation nor losing any of the logic state of the PLD. In one embodiment, data injection circuitry are added to a FIFO architecture to allow the user to inject data at random locations without disturbing the functionality of the PLD. In another embodiment, the PLD architecture is designed to provide for address wide or frame wide accessing of configuration bits. This allows for address wide configuration and reconfiguration.Type: GrantFiled: March 11, 1996Date of Patent: February 1, 2000Assignee: Altera CorporationInventors: Rakesh H. Patel, Kevin A. Norman
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Patent number: 6014334Abstract: A programmable logic device (PLD) that provides the capability to observe and control the logic state of buried internal nodes is disclosed. The PLD provides shadow storage units for internal nodes such as logic element registers, memory cells, and I/O registers. A sample/load data path includes bidirectional data buses and shift register that facilitate the sampling of internal nodes for observing their logic states, and loading of internal nodes for controlling their logic states.Type: GrantFiled: January 23, 1998Date of Patent: January 11, 2000Assignee: Altera CorporationInventors: Rakesh H. Patel, Kevin A. Norman
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Patent number: 6011744Abstract: An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.Type: GrantFiled: July 16, 1997Date of Patent: January 4, 2000Assignees: Altera Corporation, Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Michael R. Butts, Kevin A. Norman, Rakesh H. Patel, Chao Chiang Chen
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Patent number: 6011730Abstract: An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.Type: GrantFiled: April 23, 1999Date of Patent: January 4, 2000Assignees: Altera Corporation, Quickturn DesignInventors: Stephen P. Sample, Michael R. Butts, Kevin A. Norman, Rakesh H. Patel, Chao Chiang Chen
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Patent number: 5949710Abstract: A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.Type: GrantFiled: October 30, 1996Date of Patent: September 7, 1999Assignee: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright