Patents by Inventor Rakesh Jeyasingh

Rakesh Jeyasingh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Techniques to mitigate bias drift for a memory device
    Patent number: 10269396
    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Rakesh Jeyasingh, Nevil N Gajera, Mase J. Taub, Kiran Pangal
  • TECHNIQUES TO MITIGATE BIAS DRIFT FOR A MEMORY DEVICE
    Publication number: 20190057728
    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.
    Type: Application
    Filed: July 16, 2018
    Publication date: February 21, 2019
    Inventors: Rakesh JEYASINGH, Nevil N GAJERA, Mase J. TAUB, Kiran PANGAL
  • Techniques to mitigate bias drift for a memory device
    Patent number: 10026460
    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Rakesh Jeyasingh, Nevil N. Gajera, Mase J. Taub, Kiran Pangal
  • TECHNIQUES TO MITIGATE BIAS DRIFT FOR A MEMORY DEVICE
    Publication number: 20170287533
    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.
    Type: Application
    Filed: January 25, 2017
    Publication date: October 5, 2017
    Applicant: Intel Corporation
    Inventors: Rakesh Jeyasingh, Nevil N. Gajera, Mase J. Taub, Kiran Pangal
  • Techniques to mitigate bias drift for a memory device
    Patent number: 9589634
    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 7, 2017
    Assignee: Intel Corporation
    Inventors: Rakesh Jeyasingh, Nevil N. Gajera, Mase J Taub, Kiran Pangal