Abstract: Methods, apparatus, and computer programs are disclosed to detect computing system hardware defects using a portable storage device. In one embodiment, a method includes accessing a portable storage device to obtain an identifier and a set of test patterns to test a set of circuits of a computing system, the identifier to map to the set of test patterns. The method further includes determining that the set of test patterns is to be executed on the computing system based on the identifier to be obtained from accessing the portable storage device. Responsive to the determination, and executing the set of test patterns loaded from the portable storage device on the set of circuits of the computing system to detect one or more hardware defects of the set of circuits.

Abstract: Methods that are useful in semiconductor chip design are presented. A microarchitectural structured flow chart can be processed and converted into register transfer level hardware description language code. Processing of the flow chart can include detecting shapes, lines, colors, and text. The shapes that are detected can be rounded, rhombus, and rectangle and a rounded shape can represent a state, a rhombus can represent a decision, and a rectangle can represent an assignment for a finite state machine.

Abstract: Techniques and mechanisms for an integrated circuit (IC) die to support in-field testing and/or repair of a lane in a three-dimensional (3D) IC which is formed with multiple IC dies. In an embodiment, the 3D IC comprises test units which each correspond to a different partition comprising respective circuit resources. During in-field operation of the 3D IC, a given test unit is operable to detect both a first condition wherein two partitions are each in an idle state, and a second condition wherein a first link between the two partitions fails to satisfy a performance criteria. The idle states are indicated by a power management controller (PMC) agent during runtime operation of the 3D IC. In another embodiment, one or more test units configure an operational mode, based on the detected conditions, to substitute communication via the first lane with communication via a repair lane.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to perform infield testing of a system in a package. An example die includes transmit circuits to communicate via respective communication channels and control circuitry to cause a first one of the transmit circuits to send a first pattern over a first one of the communication channels. Additionally, the example control circuitry is to cause second ones of the transmit circuits to respectively send a second pattern over second respective ones of the communication channels, the second pattern being at least one of an inverse of the first pattern or identical to the first pattern.

Abstract: Methods, systems, apparatus, and articles of manufacture to validate timing constraints for an integrated circuit are disclosed. An example apparatus disclosed herein includes programmable circuitry to obtain an assumption property associated with a system on a chip (SoC) architecture, obtain a timing assertion associated with the SoC architecture, determine, using a formal property verification (FPV) tool, valid functional vectors and counter examples for the SoC architecture based on the assumption property and the timing assertion, and determine whether to accept a timing constraint based on at least one of the valid functional vectors or the counter examples, the timing constraint corresponding to the timing assertion.

Abstract: An example of an apparatus may include circuitry to monitor one or more sensors, determine a debug condition based on the monitored one or more sensors, and provide an indication of the debug condition. In some examples, the apparatus includes further circuitry to adjust a debug operation based at least in part on the provided indication of the debug condition. Other examples are disclosed and claimed.

Abstract: Techniques for debug of compute logic (e.g., a part of a system on a chip) are described. In some examples, a plurality of infield testing debug and status registers are to store information about the execution of an infield test; and a plurality of infield control debug registers are to control the infield test, wherein access to the plurality of infield testing debug registers and the plurality of infield control debug registers is programmable.

Abstract: Examples include techniques for infield testing of cryptographic circuitry located on a die. The infield testing to include providing a pass or fail status of an infield test scan of the cryptographic circuitry based on comparing an output generated by the cryptographic circuitry during a test run to a signature. The output generated by the cryptographic circuitry is in response to an input generated by a linear-feedback shift register during the test run.

Abstract: Examples include techniques for debug, survivability, and infield testing of a system-on-a-chip (SoC) or system-on-a-package (SoP) that can be configured as a processor. The techniques include using an agent coupled with a network-on-chip (NoC) fabric to launch transaction over the NoC fabric to test or debug agents, devices, or devices coupled to the SoC or SoP and/or interconnected to the NoC fabric.

Abstract: Methods and apparatus relating to intelligent sensors for high quality silicon life cycle management as well as efficient infield structural and/or functional testing are described. In an embodiment, one or more registers store configuration data. A sensor having sensor event detection logic circuitry detects an event based at least in part on one or more sensor signals and the stored configuration data. The sensor event detection logic circuitry generates a signal to cause interrupt generator logic circuitry of the sensor to generate an interrupt. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to techniques to provide secure remote debugging are described. In an embodiment, a debugging entity generates and transmits a host token to a device via an interface. The interface provides encrypted communication between the debugging entity and the device. The debugging entity generates a session key based at least in part on the host token and a device token. The debugging entity transmits an acknowledgement signal to the device after generation of the session key to initiate a debug session. The debugging entity transmits a debug unlock key to the device to cause the device to be unlocked for the debug session. Other embodiments are also disclosed and claimed.

Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to performing testing of a device while a system is operational. A device may include computing circuitry and host connectivity registers. Host connectivity registers contain configuration and memory mapping data programmed by system software upon power up of the device and computing system. The data contained in host connectivity registers should be always maintained while the computing system is operational. Scan test circuitry may be implemented, providing the ability to test the device while the system is operational. Preservation circuitry preserves or maintains the data stored in host connectivity registers allowing in-operation testing of the device, ensuring the device the ability to return to full operation at the end of in-operation testing without requiring system software to reprogram the host connectivity registers.

Abstract: Time to read the data registers in a remote Test Access Port (TAP) in a subsystem in a System-on-Chip (SoC) is reduced by reading multiple data registers in remote Test Access Ports in parallel. A Test Access Port Bridge provides access to multiple same width data registers in parallel. The same width data registers can be for the same function or different functions. The subsystems with a remote Test Access Port in the SoC can include Peripheral Component Interconnect Express (PCIe), Voltage Droop Monitors (VDMs), In-Die Variation (IDV) Monitor fub-lets, Temperature Sensors, Performance Monitors and telemetry subsystems.

Abstract: Embodiments herein relate to a test, repair, and diagnostic solution for chip-to-chip interconnects. In one aspect, on a first chip, a first finite state machine (FSM) is coupled to a set of transmit lanes. To test each transmit lane, one at a time, the first FSM is to apply a first periodic signal to a transmit lane under test and concurrently apply a second periodic signal to other transmit lanes of the set of transmit lanes, where a phase of the first periodic signal is opposite to a phase of the second periodic signal. A comparator compares a detected signal on the lane under test to an expected response. The comparator can be on the first chip, when the first chip is tested alone, or on a second chip, where the two chips are tested together.

Abstract: Techniques for interface conversion and unicast for test content, firmware, and software delivery are described. An example apparatus comprises a scan test interface coupled to multiple circuits blocks to perform a scan test for the multiple circuit blocks, and circuitry coupled to input/output (IO) signals of the scan test interface to provide content for the multiple circuit blocks and to deliver a replicated content to multiple endpoints of the multiple circuit blocks (e.g., unicast technology). In another example, the circuitry is coupled to the IO signals of the scan test interface and a system/communication interface to decode packets received at the IO signals and convert the decoded packets to provide content through the system/communication interface for the multiple circuit blocks. Other examples are described and claimed.

Abstract: Runtime memory BIST techniques are described herein. In one example, a system such as an SoC includes logic to schedule runtime testing of the memory that is non-destructive in multiple phases. Running testing of memory in multiple phases includes triggering a memory built-in self-test (BIST) testing of a subset of memory locations in a phase, where the processing logic is to pause access to the memory during the phase. The processing logic can resume access to the memory between testing phases. The next region of the memory can be tested in the phase that follows. This process can continue until the entire memory is tested, without requiring the system to be powered down.

Abstract: A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).

Abstract: A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).