Patents by Inventor Rakesh Krishnaiyer

Rakesh Krishnaiyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070106848
    Abstract: The prefetch distance to be used by a prefetch instruction may not always be correctly calculated using compile-time information. In one embodiment, the present invention generates prefetch distance calculation code to dynamically calculate a prefetch distance used by a prefetch instruction at run-time.
    Type: Application
    Filed: November 9, 2005
    Publication date: May 10, 2007
    Inventors: Rakesh Krishnaiyer, Somnath Ghosh, Abhay Kanhere
  • Patent number: 7155575
    Abstract: A computer program product determines whether a loop has a high usage count. If the computer program product determines the loop has a high usage count, the computer program product determines whether the loop has an irregularly accessed load. If the loop has an irregularly accessed load, the computer program product inserts pattern recognition code to calculate whether successive iterations of the irregular memory load in the loop have a predictable access pattern. The computer program product implants conditional adaptive prefetch code including a prefetch instruction into the output code.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventors: Rakesh Krishnaiyer, Wei Li
  • Patent number: 6880154
    Abstract: An apparatus, method, and program product for optimizing code that contains dynamically-allocated memory. The aliasing behavior of internal pointers of dynamically-allocated memory is used to disambiguate memory accesses and to eliminate false data dependencies. It is determined whether a dynamically-allocated array will behave like a statically-allocated array throughout the entire program execution once it has been allocated. This determination is used to improve the instruction scheduling efficiency, which yields better performance.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: April 12, 2005
    Assignee: Intel Corporation
    Inventors: Somnath Ghosh, Rakesh Krishnaiyer, Wei Li, Abhay Kanhere, Dattatraya Kulkarni, Chu-cheow Lim, John L. Ng
  • Publication number: 20040128661
    Abstract: An arrangement is provided for optimizing data locality for efficient memory access in code written in a non-type-safe programming language. Candidate structures in the code qualified to be optimized are first identified. Data locality optimization is then performed on such identified structures based on field re-ordering and structure splitting.
    Type: Application
    Filed: December 31, 2002
    Publication date: July 1, 2004
    Inventors: Somnath Ghosh, Rakesh Krishnaiyer, Wei Li, David Sehr
  • Publication number: 20040123041
    Abstract: A computer program product determines whether a loop has a high usage count. If the computer program product determines the loop has a high usage count, the computer program product determines whether the loop has an irregularly accessed load. If the loop has an irregularly accessed load, the computer program product inserts pattern recognition code to calculate whether successive iterations of the irregular memory load in the loop have a predictable access pattern. The computer program product implants conditional adaptive prefetch code including a prefetch instruction into the output code.
    Type: Application
    Filed: December 18, 2002
    Publication date: June 24, 2004
    Applicant: Intel Corporation
    Inventors: Rakesh Krishnaiyer, Wei Li
  • Patent number: 6721943
    Abstract: In general, the malloc-combining transformation optimization during compile-time of a source program engaged in dynamically constructing multi-dimensional arrays provides an effective method of improving cache locality by combining qualified malloc and free/realloc calls found in counted loops into a single system call and hoisting out the single call and placing it immediately preceding the beginning of the counted loops. As a result of the application of the malloc-combining optimization results in improved cache locality allows for prefetching array pointers and data elements of the dynamic arrays as if the dynamic arrays were static.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: April 13, 2004
    Assignee: Intel Corporation
    Inventors: Rakesh Krishnaiyer, Somnath Ghosh, Wei Li
  • Publication number: 20030005420
    Abstract: An apparatus, method, and program product for optimizing code that contains dynamically-allocated memory. The aliasing behavior of internal pointers of dynamically-allocated memory is used to disambiguate memory accesses and to eliminate false data dependencies. It is determined whether a dynamically-allocated array will behave like a statically-allocated array throughout the entire program execution once it has been allocated. This determination is used to improve the instruction scheduling efficiency, which yields better performance.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Inventors: Somnath Ghosh, Rakesh Krishnaiyer, Wei Li, Abhay Kanhere, Dattatraya Kulkarni, Chu-cheow Lim, John L. Ng
  • Publication number: 20020144244
    Abstract: In general, the malloc-combining transformation optimization during compile-time of a source program engaged in dynamically constructing multi-dimensional arrays provides an effective method of improving cache locality by combining qualified malloc and free/realloc calls found in counted loops into a single system call and hoisting out the single call and placing it immediately preceding the beginning of the counted loops. As a result of the application of the malloc-combining optimization results in improved cache locality allows for prefetching array pointers and data elements of the dynamic arrays as if the dynamic arrays were static.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 3, 2002
    Inventors: Rakesh Krishnaiyer, Somnath Ghosh, Wei Li