Abstract: Improved compatibility enforcement systems are provided. A candidate component request is received. A component data ingestion protocol adherence status for the candidate component is determined based on applying component data ingestion parameters of configurable adherence parameters to the candidate component output data. A configuration element protocol adherence status is determined based on applying configuration element parameters of the configurable adherence parameters to the candidate component configuration elements. One or more data transformation capabilities of the subject web application system are determined based on data outputs provided by components of a subject web application system. A system compatibility status for the candidate component is determined based on the component data ingestion protocol adherence status, the configuration element protocol adherence status, and the one or more data transformation capabilities of the subject web application system.

Abstract: A cascaded multi-loop Phase-Locked Loop (CMPLL) includes a primary loop and multiple secondary loops according to a hierarchy. The primary loop is highest in the hierarchy and each of the secondary loops is completed by components of loops higher in the hierarchy. Each loop at a lower level provides a corresponding correction signal to correct any drift from a specification frequency of a respective loop at one or more of the higher levels. The CMPLL further includes a set of bypass circuits. Each bypass circuit is coupled between a first loop and a second loop located at least one skip-level in the hierarchy, and propagates a substitute signal as the corresponding correction signal from the first loop to the second loop when a loop at the skip-level is inoperative.

Abstract: A multi-loop frequency translator (MLFT) for generating an output clock based on one or more clock sources includes multiple loops. The multiple loops include a primary loop and multiple secondary loops according to a hierarchy. The primary loop is highest in the hierarchy and each of the secondary loops is completed by components of loops higher in the hierarchy. Each loop at a lower level provides a corresponding correction signal to correct any drift from a specification frequency of a respective loop at one or more of the loops at higher levels. The primary loop is an open-loop circuit. In an embodiment, the open-loop circuit is a fractional frequency divider.

Abstract: Improved compatibility enforcement systems are provided. A candidate component request is received. A component data ingestion protocol adherence status for the candidate component is determined based on applying component data ingestion parameters of configurable adherence parameters to the candidate component output data. A configuration element protocol adherence status is determined based on applying configuration element parameters of the configurable adherence parameters to the candidate component configuration elements. One or more data transformation capabilities of the subject web application system are determined based on data outputs provided by components of a subject web application system. A system compatibility status for the candidate component is determined based on the component data ingestion protocol adherence status, the configuration element protocol adherence status, and the one or more data transformation capabilities of the subject web application system.

Abstract: A digital-to-time converter (DTC) of a fractional-n PLL contains a delay generator and a current-drawing block. The current drawn by the delay generator from the power supply contains: (A) a fixed component having a first current magnitude regardless of magnitude of a second code specifying the desired delay; and (B) a variable component having a magnitude determined only by magnitude of the second code. The current-drawing block draws correction-current from the power supply, whose magnitude is determined only by a complement of the second code.

Abstract: An integrated circuit (IC) containing a circuit to be operable using one of multiple unequal power supplies during normal operation of the IC. The IC contains a one time programmable (OTP) memory containing a first bit and a second bit, with each of the bit having an initial value and being programmable to a programmed value. A configuration engine contained in the IC operates the circuit with a first selection with respect to using one of the unequal power supplies during normal operation of the IC if both of the first bit and the second bit have an equal value comprising one of the initial value and the programmed value. The configuration engine operates the circuit with a second selection with respect to using one of the unequal power supplies during normal operation of the IC if the first bit and the second bit have unequal values.

Abstract: A Delta Sigma Modulator (DSM) includes a first memory element, a second memory element, a first adder and a second adder. The first memory element generates a sequence of sums. The second memory element generates a sequence of carries. An output of the first adder is connected to an input of the first memory element. An output of the second adder is coupled to an input of the second memory element. Multiple signal paths are formed between a start point of a set of start points and an end point of a set of end points. The set of start points include inputs to the DSM and data output of the first memory. The set of end points include inputs of the first memory element and the second memory element. Only a single one of the first adder and the second adder is present in the signal paths.

Abstract: Aspects presented herein relate to methods and devices for data or graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may configure an address range in a cache. The apparatus may also obtain a request to access data in the cache, where the request to access the data includes an address in the cache that maps to a set index in a plurality of set indexes, where an address value for the set index corresponds to a portion of the address. Further, the apparatus may select an updated address value for the set index, where the updated address value is associated with an updated address within the address range, and the updated address value corresponds to a portion of the updated address. The apparatus may also allocate the data in the request to the updated address value for the set index.

Abstract: A digital-to-time converter (DTC) is used to generate code dependent delays in fractional clock dividers by generating a fractional output clock, corresponding to a reference signal, from a divided signal having different time periods for obtaining the fractional output clock. The DTC contains an input buffer coupled to receive the divided signal and to generate an intermediate output, wherein the current drawn from a power supply contains a first average current magnitude when the divided signal has a lower time period, and a second average current magnitude when the divided signal has a higher time period. A correction-component compensates for the difference of the first average current magnitude and the second average current magnitude to improve linearity of the DTC.

Abstract: An open-loop modulator (OLM) in a fractional frequency divider. A high-pass filter is applied to residual error output of a delta-sigma modulator of the OLM. The filtering is obtained as a part of matching the signal transfer function of the combination of a portion of the DSM generating the residual error and a matching block with that of the combination of a calibration PLL and a phase detector of a gain calibration circuit contained in the OLM. The gain calibration circuit cancels a gain error of digital-to-time converter (DTC) contained in the OLM.

Abstract: A digital-to-time converter (DTC) of a fractional-n PLL contains a delay generator and a current-drawing block. The current drawn by the delay generator from the power supply contains: (A) a fixed component having a first current magnitude regardless of magnitude of a second code specifying the desired delay; and (B) a variable component having a magnitude determined only by magnitude of the second code. The current-drawing block draws correction-current from the power supply, whose magnitude is determined only by a complement of the second code.

Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

Abstract: Aspects presented herein relate to methods and devices for data or graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may configure an address range in a cache. The apparatus may also obtain a request to access data in the cache, where the request to access the data includes an address in the cache that maps to a set index in a plurality of set indexes, where an address value for the set index corresponds to a portion of the address. Further, the apparatus may select an updated address value for the set index, where the updated address value is associated with an updated address within the address range, and the updated address value corresponds to a portion of the updated address. The apparatus may also allocate the data in the request to the updated address value for the set index.

Abstract: An integrated circuit (IC) includes input/output (I/O) ports, each operating using one of a pair of unequal power supplies during normal operation of the IC. A lower supply of the pair of unequal power supplies is required to be used as the power supply for the I/O port when a first input signal to the IC is received from an external source on a first I/O port of the I/O ports. The voltage range of the logic excursions of the first input signal is greater than the range from a magnitude of the lower supply to a constant reference potential. A regulation loop derives a derived lower supply having a magnitude equaling that of the lower supply from the higher supply of the pair of unequal power supplies, and applies the derived lower supply on a power supply node of the first I/O port.

Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

Abstract: An integrated circuit (IC) includes input/output (I/O) ports, each operating using one of a pair of unequal power supplies during normal operation of the IC. A lower supply of the pair of unequal power supplies is required to be used as the power supply for the I/O port when a first input signal to the IC is received from an external source on a first I/O port of the I/O ports. The voltage range of the logic excursions of the first input signal is greater than the range from a magnitude of the lower supply to a constant reference potential. A regulation loop derives a derived lower supply having a magnitude equaling that of the lower supply from the higher supply of the pair of unequal power supplies, and applies the derived lower supply on a power supply node of the first I/O port.

Abstract: A phase-locked loop (PLL) provided according to an aspect of the present disclosure includes a phase detector, a low-pass filter, an oscillator, an output block and a phase locking block. The oscillator generates an intermediate clock and the output block generates each of successive cycles of a feedback clock on counting a pre-determined number of cycles of the intermediate clock. The phase locking block, upon detecting the PLL being out of phase-lock, controls the operation of the output block to obtain phase-lock in the PLL within two cycles of the input clock from the time of detection of the PLL being out of phase-lock.

Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.