Abstract: Systems and methods for frequency reference generation are described. In an embodiment, a frequency reference circuit, includes: a bandgap proportional to temperature (PTAT) generator circuit that generates a bandgap PTAT current; a resistor complementary to temperature (CTAT) generator circuit that generates a resistor CTAT current; an adder that adds the PTAT current and the CTAT current to generate a constant current Icons; a switched-resistor (switched-R) circuit that receives the constant current Icons and a previously generated output clock and generates an output; a bandgap voltage reference generator circuit that generates a bandgap voltage VBG; an integrator circuit that receives the output of the switched-R circuit and the bandgap voltage VBG and generates an output; and a voltage-controlled oscillator (VCO) circuit that receives the output of the integrator circuit and generates a frequency reference.

Abstract: A digital-to-analog conversion circuit (DAC) is operable to convert an input digital signal to an output analog signal. The DAC includes a digital signal processing circuit operable to process the input digital signal according to a first transfer function to generate a first processed digital signal and process the digital input signal according to a second transfer function to generate a second processed digital signal. The DAC includes a first unit DAC operable to convert the first processed digital signal to a first intermediate analog signal, and a second unit DAC operable to convert the second processed digital signal to a second intermediate analog signal. The DAC includes switching circuits and a combiner circuit to generate the output analog signal from the intermediate analog signals.

Abstract: A system includes an input shuffling circuit and digital-to-analog conversion circuitry. The input shuffling circuit includes a data input, a data output, and a control input. The input shuffling circuit is operable to receive, via the data input, an N-bit binary value, where N is an integer. The input shuffling circuit is operable to route each of the N bits of the N-bit binary word to one or more of M bits of the data output to generate an M-bit value, where M=2N, and the routing is based on a control value applied to the control input. The input shuffling circuit can be configured either in a dynamic element matching (DEM) mode or a regular binary to thermometer mode. The digital-to-analog conversion circuitry is operable to convert the M-bit value to a corresponding analog voltage and/or current. M different values of the control value may result in M different routings of the N bits of the binary word.

Abstract: A digital-to-analog conversion circuit (DAC) is operable to convert an input digital signal to an output analog signal. The DAC comprises a digital signal processing circuit operable to process the input digital signal according to a first transfer function to generate a first processed digital signal and process the digital input signal according to a second transfer function to generate a second processed digital signal. The DAC comprises a first unit DAC operable to convert the first processed digital signal to a first intermediate analog signal, and a second unit DAC operable to convert the second processed digital signal to a second intermediate analog signal. The DAC comprises switching circuits and a combiner circuit to generate the output analog signal from the intermediate analog signals.

Abstract: A system comprises an input shuffling circuit and digital-to-analog conversion circuitry. The input shuffling circuit comprises a data input, a data output, and a control input. The input shuffling circuit is operable to receive, via the data input, an N-bit binary value, where N is an integer. The input shuffling circuit is operable to route each of the N bits of the N-bit binary word to one or more of M bits of the data output to generate an M-bit value, where M=2N, and the routing is based on a control value applied to the control input. The input shuffling circuit can be configured either in a dynamic element matching (DEM) mode or a regular binary to thermometer mode. The digital-to-analog conversion circuitry is operable to convert the M-bit value to a corresponding analog voltage and/or current. M different values of the control value may result in M different routings of the N bits of the binary word.

Abstract: A system (e.g., a transmitter system on chip) comprises a digital-to-analog converter configured to convert an N-bit digital signal to a corresponding analog signal, where N is an integer greater than 1. The digital-to-analog converter may comprise N bias circuits, where each of the bias circuits is configured to generate a bias current, and route the bias current based on a value of a respective one of the N bits of the N-bit digital signal. Each of the N bias circuits may comprises a resistor network and a pair of switching circuits.

Abstract: Capacitors that can be formed fully on an integrated circuit (IC) chip are described in this disclosure. An IC chip includes a metal-oxide-silicone (MOS) capacitor formed from a MOS transistor having a drain terminal, a source terminal, a gate terminal, and a body terminal. The drain terminal and the source terminal are not electrically connected to any other node, and the gate terminal and the body terminal form respective first and second terminals of the MOS capacitor. The IC chip also includes an electrical conductor coupled to one of the gate terminal or the body terminal of the MOS transistor and configured to deliver a voltage to operate the MOS capacitor in an accumulation mode.

Abstract: Capacitors that can be formed fully on an integrated circuit (IC) chip are described in this disclosure. An IC chip includes a metal-oxide-silicone (MOS) capacitor formed from a MOS transistor having a drain terminal, a source terminal, a gate terminal, and a body terminal. The drain terminal and the source terminal are not electrically connected to any other node, and the gate terminal and the body terminal form respective first and second terminals of the MOS capacitor. The IC chip also includes an electrical conductor coupled to one of the gate terminal or the body terminal of the MOS transistor and configured to deliver a voltage to operate the MOS capacitor in an accumulation mode.