Abstract: The present disclosure provides for a hybrid DC-DC, Hybrid Variable Switched Capacitor (HVSC) power converter. The converter may include one or more power switching networks supporting a plurality of power conversion modes and characterised in that: an input terminal connected to an input power source and an associated input capacitance, an output terminal connected to a load and an associated output capacitance to obtain a desired output voltage or output load current regulation; and at least six switches, one or more inductors and one or more flying capacitors. The converter addresses the problems faced by inductor-based and inductor-less DC-DC power converters while providing higher power conversion efficiencies alike the inductor-less switched capacitor converters and voltage/current regulation alike the inductor-based power converters in a single power conversion unit and enable a duty cycle-based output voltage/current regulation.

Abstract: The present disclosure provides a system (100) and a method (200) for real-time debugging of a processor (102). The system includes a debugging unit (104) configured to receive a first set of instructions from the processor. The first set of instructions includes a set of function calls and/or a set of jump instructions. The debugging unit further includes a skip list unit (106) including a skip set of instructions. The skip list unit is configured to remove, from the first set of instructions, the skip set of instructions to generate a second set of instructions. The debugging unit includes a loop exclusion unit (108) configured to determine loops of instructions based on loop unrolling of the second set of instructions to generate a third set of instructions by removing loops of instructions from the second set of instructions. The debugging unit is configured to store the third set of instructions.

Abstract: A system for watermarking a USB Type-C and PD protocol hardware sub-system existing as a part of a SOC/IC system includes a tester to generate a watermarking signal, a device under test (DUT), wherein the DUT is configured with a USB Type-C port with power delivery implementation and including a hardware subsystem configured for watermarking the DUT and transmit a response signal upon receipt of the watermarking signal from the tester. The tester includes a controller including one or more processors that execute a set of executable instructions that are stored in a memory, upon which execution, the processor causes the controller to generate the watermarking signal, the watermarking signal comprises a custom signal and a custom packet associated with a configured custom signal stored in a data buffer that is associated with the SOC/IC system, and transmit the watermarking signal on one or more configuration channel (CC) lines.

Abstract: The present disclosure relates to an apparatus (100) for joint test action group (JTAG) and scan emulation, the apparatus includes a controller circuitry (102) that is interfaced to a target integrated circuit (IC) (106) for testing the target IC, the controller circuitry having one or more serial peripheral interface (SPI) devices (104-1, 104-2) operating in master mode and slave mode. The controller circuitry (102) operates the one or more SPI devices (104-1, 104-2) to switch between a first mode and a second mode dynamically to emulate JTAG and scan test functionality. The controller circuitry facilitates reusing the one or more SPI devices located in the controller circuitry to emulate JTAG and scan test interface protocols without any additional hardware requirements.

Abstract: The present disclosure provides a system and method for reception of BMC data in USB PD communication. The system comprises an analog block and a digital block with the digital block further comprising an idle detection mechanism, and a digital controller for rejecting noise and auto correcting of received BMC signal. The BMC data is typically processed by means of varied functions such as comparison by a threshold comparator on the analog block with programmable reference, and other components of the digital block so as to realize aspects such as noise filtering of BMC data by changing the reference dynamically based on comparison of the width of threshold comparator output signal with average signal widths which is computed during the preamble phase of USB PD communications.

Abstract: The present disclosure relates to an apparatus (100) for joint test action group (JTAG) and scan emulation, the apparatus includes a controller circuitry (102) that is interfaced to a target integrated circuit (IC) (106) for testing the target IC, the controller circuitry having one or more serial peripheral interface (SPI) devices (104-1, 104-2) operating in master mode and slave mode. The controller circuitry (102) operates the one or more SPI devices (104-1, 104-2) to switch between a first mode and a second mode dynamically to emulate JTAG and scan test functionality. The controller circuitry facilitates reusing the one or more SPI devices located in the controller circuitry to emulate JTAG and scan test interface protocols without any additional hardware requirements.

Abstract: The present disclosure provides a system (100) and a method (200) for real-time debugging of a processor (102). The system includes a debugging unit (104) configured to receive a first set of instructions from the processor. The first set of instructions includes a set of function calls and/or a set of jump instructions. The debugging unit further includes a skip list unit (106) including a skip set of instructions. The skip list unit is configured to remove, from the first set of instructions, the skip set of instructions to generate a second set of instructions. The debugging unit includes a loop exclusion unit (108) configured to determine loops of instructions based on loop unrolling of the second set of instructions to generate a third set of instructions by removing loops of instructions from the second set of instructions. The debugging unit is configured to store the third set of instructions.

Abstract: The present disclosure provides a DFT architecture for ICs and a method for testing the ICs with the proposed DFT architecture. The present disclosure also includes a focus on USB PD protocol with respect to the DFT architecture. The present disclosure also includes focus on testing IC with single I/O pin. The DFT architecture primarily comprises of a test mode controller and reuses the USBPD protocol framework logic comprising analog USBPD CC circuitry in analog block and the USBPD signaling, protocol logic in digital block for the test purposes. The DFT architecture is implemented with analog test modes and digital test modes using a single I/O pin, wherein analog test modes comprises of analog trims and observation modes and digital test modes comprises of LBIST, ATPG and digital observation modes. The method disclosed is directed to the functions associated with testing the USBPD ICS using single I/O pin.

Abstract: Systems and methods for detecting electrical connection and disconnection on an USB Type-A charging port like power adapters, power banks and car chargers having one or more USB Type-A charging port of an USB device. The system includes: a voltage source; a MOSFET SWITCH gate driver, in USB type-A connected state, that operatively couples MOSFET SWITCH with voltage source and VBUS supply of USB type-A port; charge pump; a current sense differential amplifier; and a control unit configured to: monitor VBUS current, and detect potential disconnected state of connected USB type-A port; and monitor VBUS voltage and compare VBUS voltage with predetermined voltage to sense external condition such that VBUS voltage drops because of load capacitance and load current. The control unit is further configured to, when the duty cycle has reached a minimum VBUS current, detect the USB type-A disconnection with a charge pump state.

Abstract: The present disclosure relates to an apparatus for adjusting AC-DC converter output voltage, the apparatus includes a plurality of ports, an AC-DC converter circuit, a plurality of DC-DC converters coupled to a plurality of controllers, where the plurality of controllers coupled to corresponding plurality of ports to operate the one or more loads, wherein at least one controller is a master controller and the other plurality of controllers are slave controllers. The master controller configured to determine, from the slave controllers power levels for each port, calculate an optimal input voltage value for the DC-DC converters and communicate the calculated value to the AC-DC converter circuit through a constant current source to regulate the amount of DC voltage that is being supplied to the DC-DC converters to operate the one or more loads, thereby leading to improved system efficiency of multiport USB based power adapter.

Abstract: A multiport universal serial bus (USB)-C based power supply device including a USB type-C port configured to supply power to a connected type-C external device, at least one USB type-A port configured to supply power to at least one connected type-A external sink device, a configurable power source and a controller operatively coupled with the configurable power source, the USB type-C port and at least one of the USB type-A port. The controller is configured to generate, based on the generated type-C and type-A power profile, at least one of a digital communication signal and a feedback control signal, which correspond to a power value to be supplied, based on the generated power profile, to the type-C port and the at least one type-A port respectively. Operation of the multiport USB-C based power supply device by a single controller facilitates compact construction of the multiport USB-C based power supply device.

Abstract: The present disclosure provides for a multi-ratio switched capacitor power converter. The converter may include one or more power switching networks supporting a plurality of power conversion modes and characterised in that: an input terminal connected to an input power source and an associated input capacitance, an output terminal connected to a load and an associated output capacitance to obtain a desired output voltage or output load current regulation; and a switching network with one or more arrangements of switches. The one or more arrangements can be of at least twelve, ten or nine switches to provide for a multi ratio, multi mode power conversion system that addresses the problems faced by existing power converters.

Abstract: The present disclosure relates to a system and method for enabling power sharing in a multi-port power sourcing device. The system comprises of a multiport power sourcing device having a plurality of ports and a plurality of pre-defined resistances configured to each port of the plurality of ports and is configured to receive input parameters related to plurality of ports, total power capacity of the device and maximum power of each port, determine a second set of parameters associated with pre-defined resistances, execute a first set of instructions based on the input parameters and the second set of parameters, execute a second set of instructions based on the executed first set of instructions to facilitate implementation via a request-response communication interface to discover and track any or a combination of number and status of the plurality of ports based on the determined second set of parameters.

Abstract: The present disclosure provides a bidirectional hybrid power converter that may include an input circuit consisting of an input power supply and input capacitor, a plurality of switches connected to each other, to input power supply to a set of passive electronic components, to ground and to an output circuit comprising one or more output terminals, each consisting of an output capacitance. The plurality of switches is connected directly or through passive electronic components in an arrangement to obtain a plurality of power converter networks for battery charging as well as other applications by reuse of a set of plurality of switches. The input power supply and the output load are referred to based on the direction of the power conversion flow, forward or reverse. The first terminal can be connected to both a power source as an input and load as an output.

Abstract: A system for watermarking a USB Type-C and PD protocol hardware sub-system existing as a part of a SOC/IC system includes a tester to generate a watermarking signal, a device under test (DUT), wherein the DUT is configured with a USB Type-C port with power delivery implementation and including a hardware subsystem configured for watermarking the DUT and transmit a response signal upon receipt of the watermarking signal from the tester. The tester includes a controller including one or more processors that execute a set of executable instructions that are stored in a memory, upon which execution, the processor causes the controller to generate the watermarking signal, the watermarking signal comprises a custom signal and a custom packet associated with a configured custom signal stored in a data buffer that is associated with the SOC/IC system, and transmit the watermarking signal on one or more configuration channel (CC) lines.

Abstract: The present disclosure provides for a hybrid DC-DC, Hybrid Variable Switched Capacitor (HVSC) power converter. The converter may include one or more power switching networks supporting a plurality of power conversion modes and characterised in that: an input terminal connected to an input power source and an associated input capacitance, an output terminal connected to a load and an associated output capacitance to obtain a desired output voltage or output load current regulation; and at least six switches, one or more inductors and one or more flying capacitors. The converter addresses the problems faced by inductor-based and inductor-less DC-DC power converters while providing higher power conversion efficiencies alike the inductor-less switched capacitor converters and voltage/current regulation alike the inductor-based power converters in a single power conversion unit and enable a duty cycle-based output voltage/current regulation.

Abstract: Systems and methods for detecting electrical connection and disconnection on an USB Type-A charging port like power adapters, power banks and car chargers having one or more USB Type-A charging port of an USB device. The system includes: a voltage source; a MOSFET SWITCH gate driver, in USB type-A connected state, that operatively couples MOSFET SWITCH with voltage source and VBUS supply of USB type-A port; charge pump; a current sense differential amplifier; and a control unit configured to: monitor VBUS current, and detect potential disconnected state of connected USB type-A port; and monitor VBUS voltage and compare VBUS voltage with predetermined voltage to sense external condition such that VBUS voltage drops because of load capacitance and load current. The control unit is further configured to, when the duty cycle has reached a minimum VBUS current, detect the USB type-A disconnection with a charge pump state.

Abstract: The present disclosure relates to a system and method to enable power negotiations between a Quick Charge (QC) power source with no USB power delivery (USBPD) support and a USBPD device. The proposed method identifies the support of USBPD and QC in the devices; determines the possibility of direct communication between the devices over either the D+/D?lines or the CC lines, initiates the power negotiations between USBPD device and QC power source either by translating the USBPD messages on CC line to QC signalling on the D+/D?lines and vice versa, or by handling the USBPD messages independently or combination of both; enable the fast charging of USBPD device till the maximum capacity of QC power source complying with USBPD and QC specifications.

Abstract: System and method for fault identification and fault handling in MPSD are provided. The system includes: a multi-port power sourcing device including multiple ports, a master is configured to: send a slave discovery request to multiple slave ports, receive a slave discovery response from the multiple slave ports; reset the watchdog timer in the multiple ports by sending watchdog refresh instruction periodically; each of the multiple ports experience watchdog timer timeout upon failing to receive the watchdog refresh instruction, generate their corresponding port reset upon watchdog timer timeout, to resolve one or more faults associated with the corresponding port; the multiple ports include a role change staggered timer which is triggered upon the corresponding watchdog timer timeout, and reset upon receiving the watchdog refresh instruction from master; the slave ports for which role change staggered timer times out first, changes the role to start functioning as the new master port.

Abstract: The present disclosure provides an apparatus and a method for implementing a USB-IF certified programmable power supply algorithm on a USB-C port. The method involves using a software code running on a microcontroller which monitors voltage and current being supplied by a power supply controller IC on a VBUS line of the USB-C port. Based on the detected voltage/current corrective actions are taken by the software code to bring the voltage/current to accepted levels as requested by a port partner. Further, a PPS accelerator is configured to compute an average or a new current/voltage value and provide the computed average or a new current/voltage value to a microcontroller for subsequent decision making and for other related assessment process.