Abstract: A voltage regulator includes a pass transistor coupled between an input and an output of the voltage regulator, and an amplifier having a first input configured to receive a reference voltage, and a second input coupled to the output of the voltage regulator via a feedback path. The voltage regulator also includes a voltage booster coupled between an output of the amplifier and a gate of the pass transistor, and a multiplexer having a first input configured to receive a first clock signal, a second input configured to receive a second clock signal having a higher frequency than the first clock signal, and an output coupled to a clock input of the voltage booster. The voltage regulator also includes a detection circuit having an input coupled to the amplifier, and an output coupled to a select input of the multiplexer.

Abstract: A voltage regulator includes a pass transistor coupled between an input and an output of the voltage regulator, and an amplifier having a first input configured to receive a reference voltage, and a second input coupled to the output of the voltage regulator via a feedback path. The voltage regulator also includes a voltage booster coupled between an output of the amplifier and a gate of the pass transistor, and a multiplexer having a first input configured to receive a first clock signal, a second input configured to receive a second clock signal having a higher frequency than the first clock signal, and an output coupled to a clock input of the voltage booster. The voltage regulator also includes a detection circuit having an input coupled to the amplifier, and an output coupled to a select input of the multiplexer.

Abstract: An apparatus, including: an input node to receive a signal at a pre-defined voltage; an output node; and a plurality of thin-oxide Metal Oxide-Semiconductor Field Effect Transistors (MOSFETs) coupled to the input node and to the output node, the plurality of thin-oxide MOSFETs configured to form a regenerative feedback loop to reduce the signal at the pre-defined voltage to a lower level voltage, wherein the signal at the lower level voltage is outputted through the output node.

Abstract: An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.

Abstract: An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.

Abstract: An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.

Abstract: A memory is provided with a logic gate that processes a first version and a second version of a memory clock signal to assert a clock signal for the clocking of latches in a second array of columns for the memory. The first version clocks the latches in a first array of columns for the memory. But the second version does not clock any latches in the first array of columns.

Abstract: A method includes receiving, at a model and optimization framework, a request, rendered in a first format, for a service to be implemented on a subset of a software-defined network. The request includes at least one constraint affecting implementation of the service. The method includes producing an optimized solution, rendered in a second format, for implementing the service based on the at least one constraint. The method includes translating the optimized solution to the first format and providing instructions for a cloud manager to implement the service consistent with the translated optimized solution.

Abstract: A memory is provided with a logic gate that processes a first version and a second version of a memory clock signal to assert a clock signal for the clocking of latches in a second array of columns for the memory. The first version clocks the latches in a first array of columns for the memory. But the second version does not clock any latches in the first array of columns.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for generating a negative boost voltage for memory write operations. One example memory circuit generally includes at least one memory bank, a write circuit coupled to the at least one memory bank, and a boost generation circuit coupled to the write circuit. The boost generation circuit generally includes a first node coupled to a reference potential node of the write circuit; a second node; a first capacitive element having a first terminal coupled to the first node of the boost generation circuit; a first switch configured to selectively couple the first node to a reference potential node for the memory circuit; and a second switch configured to selectively couple a second terminal of the first capacitive element to the second node of the boost generation circuit.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for generating a negative boost voltage for memory write operations. One example memory circuit generally includes at least one memory bank, a write circuit coupled to the at least one memory bank, and a boost generation circuit coupled to the write circuit. The boost generation circuit generally includes a first node coupled to a reference potential node of the write circuit; a second node; a first capacitive element having a first terminal coupled to the first node of the boost generation circuit; a first switch configured to selectively couple the first node to a reference potential node for the memory circuit; and a second switch configured to selectively couple a second terminal of the first capacitive element to the second node of the boost generation circuit.

Abstract: A method includes receiving, at a model and optimization framework, a request, rendered in a first format, for a service to be implemented on a subset of a software-defined network. The request includes at least one constraint affecting implementation of the service. The method includes producing an optimized solution, rendered in a second format, for implementing the service based on the at least one constraint. The method includes translating the optimized solution to the first format and providing instructions for a cloud manager to implement the service consistent with the translated optimized solution.

Abstract: A method includes receiving, at a model and optimization framework, a request, rendered in a first format, for a service to be implemented on a subset of a software-defined network. The request includes at least one constraint affecting implementation of the service. The method includes producing an optimized solution, rendered in a second format, for implementing the service based on the at least one constraint. The method includes translating the optimized solution to the first format and providing instructions for a cloud manager to implement the service consistent with the translated optimized solution.

Abstract: A method, computer-readable storage device and apparatus for routing traffic in a reconfigurable optical add-drop multiplexer layer of a dense wavelength division multiplexing network are disclosed. For example, the method determines the reconfigurable optical add-drop multiplexer layer has asymmetric traffic, and routes the asymmetric traffic in the reconfigurable optical add-drop multiplexer layer over a plurality of asymmetrical optical connections, wherein the plurality of asymmetrical optical connections is provided with only uni-directional equipment in the reconfigurable optical add-drop multiplexer layer.

Abstract: Systems, methods, and apparatus for writing data into a static random access memory (SRAM) are provided. A write driver circuit includes a bitcell array, a bitline coupled to the bitcell array, and a first driving circuit configured to drive the bitline via a write driver node for writing data into a bitcell for a write operation. The write driver circuit also includes a pre-charging circuit configured to control or to operate with the write driver circuit to drive the write driver node to a high voltage level or a low voltage level for the write operation, and pre-charge the write driver node to the high voltage level, and float the write driver node for a bit-masking operation.

Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a memory. The memory may include a first memory portion configured to store a first bit and generate a first data bit output. The first data bit output may be a function of the first bit when a first read enable is active. The memory may also include a second memory portion configured to store a second bit and generate a second data bit output. The second data bit output may be a function of the second bit when a second read enable is active. The memory may include a switch configured to select between the first and second bits for a read operation based on the first and second data bit outputs.

Abstract: A method includes receiving, at a model and optimization framework, a request, rendered in a first format, for a service to be implemented on a subset of a software-defined network. The request includes at least one constraint affecting implementation of the service. The method includes producing an optimized solution, rendered in a second format, for implementing the service based on the at least one constraint. The method includes translating the optimized solution to the first format and providing instructions for a cloud manager to implement the service consistent with the translated optimized solution.

Abstract: A first bitline driver includes a multiplexer for outputting data and write mask signals in functional mode, and test vector signal in test mode; a latch to latch the data signal in functional mode and the test vector signal in test mode; a latch to latch the write mask signal in functional mode and the test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell based on the data signal. A second bitline driver includes a latch to latch a data signal in functional mode if a write mask signal is deasserted and to latch a test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell.

Abstract: A write precharge period for a pseudo-dual-port memory is initiated by an edge (rising or falling) of a read precharge signal. The same edge type (rising or falling) of a write precharge signal signals the end of the write precharge period.

Abstract: A negative bit line boost circuit for a memory is configured to control a write multiplexer and a write assist transistor so that charge from a boost capacitor positively charges a bit line following a write assist period.