Patents by Inventor Rakesh L. Notani
Rakesh L. Notani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240094917Abstract: A memory control circuit coupled to multiple memory ranks may receive read and write requests for a different ranks of the multiple memory ranks. The memory control may allocate write requests to different slots based on the write requests target memory rank, and may adjust the number of slots available for a given memory rank during a write turn to improve write efficiency. The memory control circuit may also determine a number of ranks switches within a read turn based on whether a particular quality-of-service requirement associated with the read requests is being satisfied.Type: ApplicationFiled: September 19, 2023Publication date: March 21, 2024Inventors: Shane J. Keil, Gregory S. Mathews, Rakesh L. Notani
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Publication number: 20240062792Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibration, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.Type: ApplicationFiled: August 24, 2023Publication date: February 22, 2024Inventors: Robert E. Jeter, Rakesh L. Notani, Kai Lun Hsiung, Venkata Ramana Malladi, Rahul Ranjan, Naveen Kumar Korada
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Patent number: 11875871Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.Type: GrantFiled: November 9, 2022Date of Patent: January 16, 2024Assignee: Apple Inc.Inventors: Robert E. Jeter, Rakesh L. Notani, Alma L. Juarez Dominguez
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Patent number: 11776597Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.Type: GrantFiled: January 3, 2022Date of Patent: October 3, 2023Assignee: Apple Inc.Inventors: Robert E. Jeter, Rakesh L. Notani, Kai Lun Hsiung, Venkata Ramana Malladi, Rahul Ranjan, Naveen Kumar Korada
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Publication number: 20230115215Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.Type: ApplicationFiled: November 9, 2022Publication date: April 13, 2023Inventors: Robert E. Jeter, Rakesh L. Notani, Alma L. Juarez Dominguez
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Patent number: 11527269Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.Type: GrantFiled: December 17, 2019Date of Patent: December 13, 2022Assignee: Apple Inc.Inventors: Robert E. Jeter, Rakesh L. Notani, Alma L. Juarez Dominguez
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Patent number: 11501820Abstract: A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.Type: GrantFiled: February 22, 2021Date of Patent: November 15, 2022Assignee: Apple Inc.Inventors: Robert E. Jeter, Kai Lun Hsiung, Rakesh L. Notani, Venkata Ramana Malladi, John H. Kelm, Taehyun Kim
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Publication number: 20220270664Abstract: A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.Type: ApplicationFiled: February 22, 2021Publication date: August 25, 2022Inventors: Robert E. Jeter, Kai Lun Hsiung, Rakesh L. Notani, Venkata Ramana Malladi, John H. Kelm, Taehyun Kim
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Publication number: 20220189519Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.Type: ApplicationFiled: January 3, 2022Publication date: June 16, 2022Inventors: Robert E. Jeter, Rakesh L. Notani, Kai Lun Hsiung, Venkata Ramana Malladi, Rahul Ranjan, Naveen Kumar Korada
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Patent number: 11226752Abstract: Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.Type: GrantFiled: March 5, 2019Date of Patent: January 18, 2022Assignee: Apple Inc.Inventors: Rakesh L. Notani, Robert E. Jeter, Suhas Kumar Suvarna Ramesh, Naveen Kumar Korada, Mohammad Rizwan, Alma L. Juarez Dominguez, John H. Kelm, Matthew R. Johnson
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Patent number: 11221798Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.Type: GrantFiled: January 24, 2020Date of Patent: January 11, 2022Assignee: Apple Inc.Inventors: Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Peter Fu, Rakesh L. Notani, Sukalpa Biswas, Thejasvi Magudilu Vijayaraj, Yanzhe Liu, Shane J. Keil
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Patent number: 11217285Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.Type: GrantFiled: August 5, 2020Date of Patent: January 4, 2022Assignee: Apple Inc.Inventors: Robert E. Jeter, Rakesh L. Notani, Kai Lun Hsiung, Venkata Ramana Malladi, Rahul Ranjan, Naveen Kumar Korada
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Publication number: 20210183414Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Inventors: Robert E. Jeter, Rakesh L. Notani, Alma L. Juarez Dominguez
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Patent number: 10991403Abstract: A method and apparatus for performing memory calibration with endpoint replay is disclosed. A first calibration of a data strobe signal in a memory subsystem is performed. The first calibration includes determining initial values of first and second endpoints indicative of first and second delay values, respectively, applied to the data strobe signal. A second calibration of the data strobe signal is performed around these endpoints, within a range thereof that is less than a full range there between. Based on the second calibration, the endpoints are adjusted.Type: GrantFiled: February 15, 2019Date of Patent: April 27, 2021Assignee: Apple Inc.Inventors: Robert E. Jeter, Rakesh L. Notani, Venkata R. Malladi
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Patent number: 10877688Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.Type: GrantFiled: August 1, 2016Date of Patent: December 29, 2020Assignee: Apple Inc.Inventors: Manu Gulati, Peter F. Holland, Erik P. Machnicki, Robert E. Jeter, Rakesh L. Notani, Neeraj Parik, Marc A. Schaub
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Patent number: 10872652Abstract: A method and apparatus for optimizing calibrations of a memory subsystem is disclosed. A memory controller of a memory subsystem includes a memory interface suitable for coupling to a DRAM having a plurality of banks. The memory controller includes a state machine the state machine may initiate calibration of circuitry within the memory controller. Responsive to initiating the calibration, the state machine also causes a refresh command to be transmitted to the DRAM. The calibration is then performed concurrent with the refresh of the DRAM. Subsequent to transmitting the refresh command, the state machine causes the memory interface to be placed into a low power state.Type: GrantFiled: June 19, 2018Date of Patent: December 22, 2020Assignee: Apple Inc.Inventors: Rakesh L. Notani, Lakshmi Narasimha Murthy Nukala, Kai Lun Hsiung, Sukalpa Biswas, Yanzhe Liu
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Publication number: 20200285406Abstract: Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.Type: ApplicationFiled: March 5, 2019Publication date: September 10, 2020Inventors: Rakesh L. Notani, Robert E. Jeter, Suhas Kumar Suvarna Ramesh, Naveen Kumar Korada, Mohammad Rizwan, Alma L. Juarez Dominguez, John H. Kelm, Matthew R. Johnson
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Publication number: 20200266810Abstract: A method and apparatus for performing duty cycle correction with read/write calibrations is disclosed. A first calibration is performed in a memory subsystem having a memory and a memory controller. The first calibration includes conveying a first clock signal from the memory controller to the memory, and determining the duty cycle of the first clock signal. If the duty cycle is not within a specified range, the duty cycle is adjusted and the process repeated. After the duty cycle of the first clock signal is within the specified range, a second calibration is performed, the second calibration including conveying a second clock signal from the memory to the memory controller. The duty cycle of the first clock signal may be further adjusted based on the second calibration.Type: ApplicationFiled: February 15, 2019Publication date: August 20, 2020Inventors: Robert E. Jeter, Rakesh L. Notani, Kai Lun Hsiung, Yanzhe Liu
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Publication number: 20200265881Abstract: A method and apparatus for performing memory calibration with endpoint replay is disclosed. A first calibration of a data strobe signal in a memory subsystem is performed. The first calibration includes determining initial values of first and second endpoints indicative of first and second delay values, respectively, applied to the data strobe signal. A second calibration of the data strobe signal is performed around these endpoints, within a range thereof that is less than a full range there between. Based on the second calibration, the endpoints are adjusted.Type: ApplicationFiled: February 15, 2019Publication date: August 20, 2020Inventors: Robert E. Jeter, Rakesh L. Notani, Venkata R. Malladi
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Patent number: 10734983Abstract: A method and apparatus for performing duty cycle correction with read/write calibrations is disclosed. A first calibration is performed in a memory subsystem having a memory and a memory controller. The first calibration includes conveying a first clock signal from the memory controller to the memory, and determining the duty cycle of the first clock signal. If the duty cycle is not within a specified range, the duty cycle is adjusted and the process repeated. After the duty cycle of the first clock signal is within the specified range, a second calibration is performed, the second calibration including conveying a second clock signal from the memory to the memory controller. The duty cycle of the first clock signal may be further adjusted based on the second calibration.Type: GrantFiled: February 15, 2019Date of Patent: August 4, 2020Assignee: Apple Inc.Inventors: Robert E. Jeter, Rakesh L. Notani, Kai Lun Hsiung, Yanzhe Liu