Abstract: Various aspects are described herein. In some aspects, the disclosure provides techniques for accessing tag information in a memory line. The techniques include determining an operation to perform on at least one memory line of a memory. The techniques further include performing the operation by accessing only a portion of the at least one memory line, wherein the only the portion of the at least one memory line comprises one or more flag bits that are independently accessible from remaining bits of the at least one memory line.

Abstract: A graphical user interface (“GUI”) allows for the creation of custom key performance indicators (“KPIs”) for real-time analysis of network telemetry events. The GUI can include options for defining variables based on event attributes. These can correspond to events that exist in input telemetry streams at a stream processor. The GUI can allow creation of a formula based on these variables. An aggregation section specifies how the output of the formula is aggregated. This can be based on group, aggregation function, and time period. A manager process causes the stream processor to apply the custom KPI definition to real-time input streams. An output KPI stream can then be routed to a destination for analysis.

Abstract: Systems and methods for providing mobile network guidance to applications communicating with devices via a mobile network.

Abstract: Method and Apparatus for automatically switching to a low power retention mode based on architectural clock gating is disclosed. In some implementations, a system includes a central processing unit (CPU), comprising a clock gating cell configured to receive a clock enable signal. The system further includes a switching module configured to monitor the clock enable signal and to cause a power manager to switch the CPU from a first power supply output to a second power supply output in response to the clock enable signal changing from a first state to a second state.

Abstract: Various aspects are described herein. In some aspects, the disclosure provides techniques for accessing tag information in a memory line. The techniques include determining an operation to perform on at least one memory line of a memory. The techniques further include performing the operation by accessing only a portion of the at least one memory line, wherein the only the portion of the at least one memory line comprises one or more flag bits that are independently accessible from remaining bits of the at least one memory line.

Abstract: A system and method for training and executing an adaptive bitrate (ABR) controller can include clustering content into content clusters based on content metadata, clustering network scenarios based on network information, normalizing input measurements, training the ABR controller for each content within at least one of a given content cluster and a given network scenario cluster by determining network information and network metadata, associated with the respective content, determining a content bitrate, determining a reward associated with the content bitrate, and training the ABR controller based on the reward.

Abstract: A graphical user interface (“GUI”) allows for the creation of custom key performance indicators (“KPIs”) for real-time analysis of network telemetry events. The GUI can include options for defining variables based on event attributes. These can correspond to events that exist in input telemetry streams at a stream processor. The GUI can allow creation of a formula based on these variables. An aggregation section specifies how the output of the formula is aggregated. This can be based on group, aggregation function, and time period. A manager process causes the stream processor to apply the custom KPI definition to real-time input streams. An output KPI stream can then be routed to a destination for analysis.

Abstract: A method for automated root cause analysis in mobile radio access networks, including: determining mobile radio access network data (e.g., RAN data); detecting an anomaly for a set of user sessions and/or cells from the RAN data; and classifying the detected anomalies using a set of root cause classifiers.

Abstract: Systems and methods for providing mobile network guidance to applications communicating with devices via a mobile network.

Abstract: Systems, methods, and apparatus for operating a central processing unit (CPU) are provided. The CPU includes a plurality of memories including a first group of memories and a second group of memories. The plurality of memories are grouped based on a timing criticality of each memory. The CPU further includes a memory core (MX) voltage supply configured to provide the plurality of memories with an MX voltage, an application processor core (APC) voltage supply configured to provide the plurality of memories with an APC voltage, and a voltage switching circuit. The voltage switching circuit detects an operating mode of the CPU and switches a voltage provided to at least one of the first group of memories or the second group of memories between the MX voltage and the APC voltage based on a type of the operating mode detected.

Abstract: Method and Apparatus for automatically switching to a low power retention mode based on architectural clock gating is disclosed. In some implementations, a system includes a central processing unit (CPU), comprising a clock gating cell configured to receive a clock enable signal. The system further includes a switching module configured to monitor the clock enable signal and to cause a power manager to switch the CPU from a first power supply output to a second power supply output in response to the clock enable signal changing from a first state to a second state.

Abstract: Systems, methods, and apparatus for operating a central processing unit (CPU) are provided. The CPU includes a plurality of memories including a first group of memories and a second group of memories. The plurality of memories are grouped based on a timing criticality of each memory. The CPU further includes a memory core (MX) voltage supply configured to provide the plurality of memories with an MX voltage, an application processor core (APC) voltage supply configured to provide the plurality of memories with an APC voltage, and a voltage switching circuit. The voltage switching circuit detects an operating mode of the CPU and switches a voltage provided to at least one of the first group of memories or the second group of memories between the MX voltage and the APC voltage based on a type of the operating mode detected.

Abstract: In some aspects, a method for managing leakage power includes coupling a first supply rail to a cache memory if a processor is in a first performance mode, wherein the processor accesses the cache memory, and coupling a second supply rail to the cache memory if the processor is in a second performance mode. The method also includes detecting gating of a clock signal to the cache memory or the processor, and, upon detecting gating of the clock signal, switching the cache memory from the second supply rail to the first supply rail if the cache memory is currently coupled to the second supply rail.

Abstract: In some aspects, a method for managing leakage power includes coupling a first supply rail to a cache memory if a processor is in a first performance mode, wherein the processor accesses the cache memory, and coupling a second supply rail to the cache memory if the processor is in a second performance mode. The method also includes detecting gating of a clock signal to the cache memory or the processor, and, upon detecting gating of the clock signal, switching the cache memory from the second supply rail to the first supply rail if the cache memory is currently coupled to the second supply rail.

Abstract: An apparatus includes a first circuit configured to receive one or more requests from a plurality of cores. Each of the one or more requests is to enter or to exit one of a plurality of power-down modes. The first circuit further selects one or more of the cores to enter or to exit the requested power-down mode or modes based on inrush current information associated with the power-down modes. A second circuit is configured to effect entering or exiting the requested power-down mode or modes in the selected one or more of the cores.

Abstract: An apparatus includes a first circuit configured to receive one or more requests from a plurality of cores. Each of the one or more requests is to enter or to exit one of a plurality of power-down modes. The first circuit further selects one or more of the cores to enter or to exit the requested power-down mode or modes based on inrush current information associated with the power-down modes. A second circuit is configured to effect entering or exiting the requested power-down mode or modes in the selected one or more of the cores.