Patents by Inventor Rakesh N. Joshi

Rakesh N. Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Linking addressable shadow port and protocol for serial bus networks
    Patent number: 7353307
    Abstract: Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or protocol bypass inputs. Multiple LASPs are cascaded and the connection of their secondary TAPs are configured using the LASP protocol or protocol bypass inputs.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: April 1, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Rakesh N. Joshi, Mark S. Gary, Kenneth L. Williams
  • Linking addressable shadow port and protocol for serial bus networks
    Patent number: 7177965
    Abstract: Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or protocol bypass inputs. Multiple LASPs are cascaded and the connection of their secondary TAPs are configured using the LASP protocol or protocol bypass inputs.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: February 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Rakesh N. Joshi, Mark S. Gary, Kenneth L. Williams
  • Linking addressable shadow port and protocol for serial bus networks
    Patent number: 6968408
    Abstract: Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or protocol bypass inputs. Multiple LASP are cascaded and the connection of their secondary TAPs are configured using the LASP protocol or protocol bypass inputs.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: November 22, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Rakesh N. Joshi, Mark S. Gary, Kenneth L. Williams
  • Linking addressable shadow port and protocol for serial bus networks
    Publication number: 20040037303
    Abstract: Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or protocol bypass inputs. Multiple LASP are cascaded and the connection of their secondary TAPs are configured using the LASP protocol or protocol bypass inputs.
    Type: Application
    Filed: December 30, 2002
    Publication date: February 26, 2004
    Inventors: Rakesh N. Joshi, Mark S. Gary, Kenneth L. Williams
  • Fast FiFo memory storage system
    Patent number: 6366529
    Abstract: A fast FIFO memory system stores identical data in both static RAM memory and FIFO memory. Data is transferred from the FIFO when insufficient RAM read time is available. When the FIFO is full, additional data is stored in the RAM which runs at a much slower speed than the FIFO. Data is then transferred from the RAM until the FIFO is no longer full, at which time the memory system again functions at the faster FIFO speed.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: April 2, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth L. Williams, Rakesh N. Joshi
  • Fast reprogrammable FIFO status flags system
    Patent number: 6345008
    Abstract: A reprogrammable FIFO status flags system for determining the status of a FIFO memory having a storage capacity (depth) D generates a pair of FIFO status flags, PAF (Programmable Almost Full) and PAE (Programmable Almost Empty) that can be reprogrammed multiple times, even after FIFO writes and reads have occurred. Two offset values (‘N’ and ‘M’) are programmed into the FIFO. PAE is high only when the number of words stored in the FIFO equals N or fewer. PAF is high only when the number of words stored in the FIFO equals D minus M or more.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: February 5, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth L. Williams, Rakesh N. Joshi