Patents by Inventor Rakesh Yaraduyathinahalli Channabasappa

Rakesh Yaraduyathinahalli Channabasappa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Filler bank control circuit for synchronous FIFO queues and other memory devices
    Patent number: 10095474
    Abstract: An apparatus includes a controller and logic circuitry. The controller is configured to generate multiple single-bit logic values. Each single-bit logic value has one of (i) a first value indicating that a data packet has been written into a memory and (ii) a second value indicating that a data packet has been read from the memory. The logic circuitry is configured to serially stack the single-bit logic values. The apparatus could further include a shift memory bank configured to store the single-bit logic values. The logic circuitry can be configured to serially stack the single-bit logic values in the shift memory bank. For example, the logic circuitry can be configured to shift the single-bit logic values in the shift memory bank in different directions and insert one single-bit logic value into the memory bank at different ends depending on whether the one logic value has the first or second value.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: October 9, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rakesh Yaraduyathinahalli Channabasappa, Shekhar Dinkar Patil, Rajeev Suvarna
  • FILLER BANK CONTROL CIRCUIT FOR SYNCHRONOUS FIFO QUEUES AND OTHER MEMORY DEVICES
    Publication number: 20150317087
    Abstract: An apparatus includes a controller and logic circuitry. The controller is configured to generate multiple single-bit logic values. Each single-bit logic value has one of (i) a first value indicating that a data packet has been written into a memory and (ii) a second value indicating that a data packet has been read from the memory. The logic circuitry is configured to serially stack the single-bit logic values. The apparatus could further include a shift memory bank configured to store the single-bit logic values. The logic circuitry can be configured to serially stack the single-bit logic values in the shift memory bank. For example, the logic circuitry can be configured to shift the single-bit logic values in the shift memory bank in different directions and insert one single-bit logic value into the memory bank at different ends depending on whether the one logic value has the first or second value.
    Type: Application
    Filed: May 5, 2014
    Publication date: November 5, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Rakesh Yaraduyathinahalli Channabasappa, Shekhar Dinkar Patil, Rajeev Suvarna