Abstract: Methods, systems, and devices for prioritizing refresh operations of a memory system are described. In some instances, a memory system may refresh one or more production state awareness (PSA) blocks at power-on. In some cases, the PSA blocks that are refreshed may have relatively high bit error rates (BERs). For example, PSA blocks with relatively high BERs that are not refreshed may increase the risk of system failure or malfunction. Other PSA blocks may not be refreshed at power-on, and may instead be refreshed at a later time based on one or more criteria in order to prioritize refreshing the PSA blocks having relatively high BERs.

Abstract: Methods, systems, and devices for zone write operation techniques are described. A memory system may support zone write operations directly to a multiple-level cell cursor of the memory system. For example, the memory system may close a first zone associated with storing a first type of information from being written with additional information. Based on closing the first zone, the memory system may determine a rate at which the first type of information is written to the memory system. The memory system may receive a command to write second information of the first type to a second zone of the memory system. To write the second information to the second zone, the memory system may write the second information to a cursor configured to store information written to the second zone, and the cursor may be associated with multiple-level memory cells based on the first rate.

Abstract: Methods, systems, and devices for a common error protection buffer for multiple cursors are described. A memory device may receive a command to write data to a memory system. The memory device may assign portions of the data to respective pages of a first cursor and generate error protection data for the assigned data. The memory device may assign the generated error protection data to an error protection buffer common to multiple cursors, for example, by performing an combination operation. The memory device may increment a counter associated with the error protection buffer. The memory device may write a summary of contents of the error protection buffer and a position of each cursor related to the error protection data based on the counter satisfying a threshold. The memory device may perform a readback operation to facilitate garbage collection without losing error protection data.

Abstract: Methods, systems, and devices for sequential write operations using multiple memory dies are described. A memory system may be configured to support write operations that include writing respective subsets of a sequence of data to each first memory die of a set of multiple first memory dies, and then writing the sequence of data to a second memory die (e.g., based on reading the respective subsets of the sequence of data from the set of first memory dies). In some examples, such techniques may be implemented with memory dies having different memory cell storage densities. For example, the set of multiple first memory dies may be operated in accordance with relatively lower storage densities to leverage relatively faster access operations, whereas the second memory die may be operated in accordance with a relatively higher storage density to leverage relatively higher capacity.

Abstract: Methods, systems, and devices for data storage during power state transition of a memory system are described. A memory system may receive a command indicating a transition from a first power state to a second power state or a third power state. Upon receiving the command, the memory system may write a first set of data to a volatile memory of the memory system. For example, the first set of data may be a snapshot or a copy of one or more elements of a second set of data. The memory system may flush the first set of data from the volatile memory to a non-volatile memory of the memory system. The memory system may transition from the first power state to the second power state or the third power state and read the snapshot from the volatile memory or the non-volatile memory upon transitioning back to the first power state.

Abstract: Methods, systems, and devices for data relocation scheme selection for a memory system are described. A system may select, based on a fragmentation characteristic of data associated with a block of addresses, whether to perform a relocation associated with relocating invalid data, or to perform a relocation associated with refraining from relocating invalid data. A relocation associated with relocating invalid data may be selected for relatively more-fragmented data, which may avoid a relatively higher latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a more-granular level.

Abstract: Techniques for memory operations are described. Indications of temperature levels at a memory device may be received, where each of the indications may be associated with a respective time point. Based on an indicated temperature level satisfying a first threshold, a derivative of a temperature of the memory device may be calculated using the indicated temperature levels. Based on calculating the derivative, a determination as to whether the derivative satisfies a second threshold may be determined. If the derivative satisfies the second threshold, operations for accessing the memory device may be modified. A second derivative of the temperature of the memory device may similarly be calculated and compared against a third threshold based on the indicated temperature level satisfying the first threshold. If the second derivative satisfies the third threshold, operations for accessing the memory device may be modified by a different amount.