Patents by Inventor Rakshit Singhal

Rakshit Singhal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100153759
    Abstract: A method and apparatus of a power gating technique to reduce power in functional and test modes are disclosed. In one embodiment, a method includes separating a power domain of a module to two distinctive sets of sub-power domains, powering a combinational logic with one of the two distinctive sets of power domains, and powering a sequential logic with the other of the two distinctive sets of power domains. The method may reduce an active and leakage power in a functional mode by gating power of the combinational logic and not gating power of the sequential logic. A system state may be retained in the sequential logic because the sequential logic remains powered during the functional mode without requiring a retention flop, an on-chip memory and/or an off-chip memory. A wake up time of the module may be reduced through the retention of the system state in the sequential logic.
    Type: Application
    Filed: December 15, 2008
    Publication date: June 17, 2010
    Inventor: RAKSHIT SINGHAL
  • Patent number: 7200690
    Abstract: Enhancing the throughput rate of a memory access system by using store and forward buffers (SFB) in combination with a DMA engine. According to an aspect of the present invention, the worst case throughput rate (without use of SFBs) is computed, and maximization factor equaling a desired throughput rate divided by the worst case throughput rate is computed. A number of SFBs is determined as equaling one less than the maximization factor. By placing the SFBs at appropriate locations in the data transfer path, the desired throughput rate may be attained when transferring large volumes of data.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: April 3, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Rakshit Singhal, Anindya Saha
  • Publication number: 20040213054
    Abstract: Enhancing the throughput rate of a memory access system by using store and forward buffers (SFB) in combination with a DMA engine. According to an aspect of the present invention, the worst case throughput rate (without use of SFBs) is computed, and maximization factor equaling a desired throughput rate divided by the worst case throughput rate is computed. A number of SFBs is determined as equaling one less than the maximization factor. By placing the SFBs at appropriate locations in the data transfer path, the desired throughput rate may be attained when transferring large volumes of data.
    Type: Application
    Filed: April 22, 2004
    Publication date: October 28, 2004
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rakshit SINGHAL, Anindya SAHA