Abstract: A MEMORY TEST METHODOLOGY is disclosed. The memory is checkerboarded and divided into blocks, the cells of which are scrambled by a EEPROM. The memory is the assaulted. After each assault, one block (time-test) is tested in alternation with each of the other blocks (space-test) by reading each cell of the clock, comparing it with the checkerboard, and writing the opposite of the checkerboard to the cell. When this process has been completed for all blocks, it is repeated, this time writing the checkerboard to each cell. Failures are noted on a fast capture RAM. This cycle is repeated several times. The data is displayed, and the memory is assaulted again. It is re-checkerboarded immediately before the assault. Errors in the time test block are displayed separately from those in the space-test blocks, and both displays are repeated in the same format after each assault.

Abstract: An interface between a memory tester and a memory includes, in order, an inverter and digital line driver, a short section of coaxial cable, an impedance matching resistor, a level shifter (which may be omitted if the tester and the memory operate at a common voltage), an analog line driver, a long section of coaxial cable, and a final impedance matching resistor. Very high frequency memory interrogation is supported.