Patents by Inventor Ralf Detlef Schaefer

Ralf Detlef Schaefer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DSP-based data recovery
    Patent number: 7656982
    Abstract: A bit clock recovery apparatus for digital storage readout employing sync frames, where an oversampled readout signal is stored in memory, sync patterns are located in the signal using DSP means, distances of consecutive sync pattern locations are calculated, and bit clock is recovered from these distances and the knowledge about the data framing structure.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: February 2, 2010
    Assignee: Thomson Licensing
    Inventors: Klaus Gaedke, Friedrich Timmermann, Axel Kochale, Ralf-Detlef Schaefer, Herbert Schütze, Marten Kabutz
  • Switchable PLL circuit
    Patent number: 7576576
    Abstract: An electronic circuit includes a first and a second PLL stage (PLL1, PLL2) that can be switched in parallel or in series depending on locking of the first one of the PLL circuits to an input signal (IN). When in parallel, only the second PLL circuit (PLL2) is actively supplying a clock signal to the output of the electronic circuit. The first PLL circuit (PLL1) continues trying to lock onto the input signal (IN). A lock detector (LD) monitors the locking status of the first PLL circuit (PLL1) to the input signal (IN) and, upon locking, sets switches (S1, S2) to couple the output of the first PLL circuit (PLL1) to the input of the second PLL circuit (PLL2), and to couple the output of the second PLL circuit (PLL2) to the input of the first PLL circuit (PLL1).
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: August 18, 2009
    Assignee: Thomson Licensing
    Inventors: Michael Drexler, Ralf-Detlef Schaefer
  • Switchable PLL circuit
    Publication number: 20070103214
    Abstract: An electronic circuit includes a first and a second PLL stage (PLL1, PLL2) that can be switched in parallel or in series depending on locking of the first one of the PLL circuits to an input signal (IN). When in parallel, only the second PLL circuit (PLL2) is actively supplying a clock signal to the output of the electronic circuit. The first PLL circuit (PLL1) continues trying to lock onto the input signal (IN). A lock detector (LD) monitors the locking status of the first PLL circuit (PLL1) to the input signal (IN) and, upon locking, sets switches (S1, S2) to couple the output of the first PLL circuit (PLL1) to the input of the second PLL circuit (PLL2), and to couple the output of the second PLL circuit (PLL2) to the input of the first PLL circuit (PLL1).
    Type: Application
    Filed: November 7, 2006
    Publication date: May 10, 2007
    Inventors: Michael Drexler, Ralf-Detlef Schaefer
  • Dsp-based data recovery
    Publication number: 20070064847
    Abstract: A bit clock recovery apparatus for digital storage readout employing sync frames, where an oversampled readout signal is stored in memory, sync patterns are located in the signal using DSP means, distances of consecutive sync pattern locations are calculated, and bit clock is recovered from these distances and the knowledge about the data framing structure.
    Type: Application
    Filed: April 27, 2004
    Publication date: March 22, 2007
    Inventors: Klaus Gaedke, Friedrich Timmermann, Axel Kochale, Ralf-Detlef Schaefer, Herbert Schutze, Marten Kabutz
  • Cartridge for camera
    Patent number: D566714
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: April 15, 2008
    Assignee: Thomson Licensing S.A.
    Inventors: Ralf Detlef Schaefer, Wolfgang Metje