Abstract: Techniques for establishing a network connection via a physical medium after exiting a low-power state. The technique includes receiving circuit configuration information for configuring a circuit for establishing a network connection via a physical medium. The technique also includes determining first redundancy information based on the circuit configuration information. The technique also includes storing the determined first redundancy information and the circuit configuration information. The technique also includes entering, by the circuit, a low-power state, and exiting the low-power state. The technique also includes determining second redundancy information based on the stored circuit configuration information after the circuit has exited the low-power state. The technique also includes comparing the second redundancy information to the first redundancy information. The technique also includes detecting an error based on the comparing.

Abstract: Techniques for establishing a network connection via a physical medium after exiting a low-power state. The technique includes receiving circuit configuration information for configuring a circuit for establishing a network connection via a physical medium. The technique also includes determining first redundancy information based on the circuit configuration information. The technique also includes storing the determined first redundancy information and the circuit configuration information. The technique also includes entering, by the circuit, a low-power state, and exiting the low-power state. The technique also includes determining second redundancy information based on the stored circuit configuration information after the circuit has exited the low-power state. The technique also includes comparing the second redundancy information to the first redundancy information. The technique also includes detecting an error based on the comparing.

Abstract: Disclosed embodiments include an Ethernet PHY device comprising a serial communication interface adapted to be coupled to a microcontroller, a register set having registers, and a checksum generator circuit coupled to the register set and configured to calculate a current checksum. The embodiment also includes a checksum register that is coupled to the checksum generator and is configured to store the current checksum. It further includes a checksum checker that is coupled to the checksum generator, the checksum register and the microcontroller, and is configured to compare a previous value of the checksum to the current checksum and, responsive to the previous value being different than the current checksum, send an error report to the microcontroller. The embodiment also includes a trigger circuit coupled to the checksum generator configured to send a checksum start signal to the checksum generator.

Abstract: Disclosed embodiments include an Ethernet PHY device comprising a serial communication interface adapted to be coupled to a microcontroller, a register set having registers, and a checksum generator circuit coupled to the register set and configured to calculate a current checksum. The embodiment also includes a checksum register that is coupled to the checksum generator and is configured to store the current checksum. It further includes a checksum checker that is coupled to the checksum generator, the checksum register and the microcontroller, and is configured to compare a previous value of the checksum to the current checksum and, responsive to the previous value being different than the current checksum, send an error report to the microcontroller. The embodiment also includes a trigger circuit coupled to the checksum generator configured to send a checksum start signal to the checksum generator.

Abstract: Method and apparatus for serial data transfer between at least two modules (10, 12) connected to each other by way of a serial data bus (18) where the data transfer is governed by a clock signal (CLK). The modules (10, 12) each comprise a receiver unit (30) for the reception of the data and a transmitter unit (22) for the transmission of data. The output of a data value by the transmitter unit (22) of one module (12) to another module (10) at the serial data bus (18), and the import of the data value by the receiver unit (30) of the corresponding other module (10) are initiated by slopes of the clock signal (CLK). The clock signal that triggers the transmission of this data value in the one module (12) is delayed via a delay element (38) one pulse repetition period (?TP) of the clock signal (CLK).

Abstract: In a serial interface unit (10) for the transmission and reception of data under the control of clock signals, the data are output from a data source to a data output (24) via an output driver (22). A transmit monitor (52) compares the data supplied by the data source with the data received at the data output (24) via the output driver (22). The transmit monitor outputs an error signal when the data so compared do not coincide.

Abstract: Method and apparatus for serial data transfer between at least two modules (10, 12) connected to each other by way of a serial data bus (18) where the data transfer is governed by a clock signal (CLK). The modules (10, 12) each comprise a receiver unit (30) for the reception of the data and a transmitter unit (22) for the transmission of data. The output of a data value by the transmitter unit (22) of one module (12) to another module (10) at the serial data bus (18), and the import of the data value by the receiver unit (30) of the corresponding other module (10) are initiated by slopes of the clock signal (CLK). The clock signal that triggers the transmission of this data value in the one module (12) is delayed via a delay element (38) one pulse repetition period (ATP) of the clock signal (CLK).

Abstract: In a serial interface unit (10) for the transmission and reception of data under the control of clock signals, the data are output from a data source to a data output (24) via an output driver (22). A transmit monitor (52) compares the data supplied by the data source with the data received at the data output (24) via the output driver (22). The transmit monitor outputs an error signal when the data so compared do not coincide.