Patents by Inventor Ralf Goettsche

Ralf Goettsche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for a partial-address select-signal generator with address shift
    Patent number: 9411724
    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing and using a partial-address select-signal generator with address shift.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: August 9, 2016
    Assignee: Intel Corporation
    Inventors: Lutz Naethke, Eric Desmarais, Ralf Goettsche
  • Adaptive data prefetching
    Patent number: 9280474
    Abstract: A system and method for adaptive data prefetching in a processor enables adaptive modification of parameters associated with a prefetch operation. A stride pattern in successive addresses of a memory operation may be detected, including determining a stride length (L). Prefetching of memory operations may be based on a prefetch address determined from a base memory address, the stride length L, and a prefetch distance (D). A number of prefetch misses may be counted at a miss prefetch count (C). Based on the value of the miss prefetch count C, the prefetch distance D may be modified. As a result of adaptive modification of the prefetch distance D, an improved rate of cache hits may be realized.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: March 8, 2016
    Assignee: Intel Corporation
    Inventors: Demos Pavlou, Pedro Lopez, Mirem Hyuseinova, Fernando Latorre, Steffen Kosinski, Ralf Goettsche, Varun K. Mohandru
  • ADAPTIVE DATA PREFETCHING
    Publication number: 20150143057
    Abstract: A system and method for adaptive data prefetching in a processor enables adaptive modification of parameters associated with a prefetch operation. A stride pattern in successive addresses of a memory operation may be detected, including determining a stride length (L). Prefetching of memory operations may be based on a prefetch address determined from a base memory address, the stride length L, and a prefetch distance (D). A number of prefetch misses may be counted at a miss prefetch count (C). Based on the value of the miss prefetch count C, the prefetch distance D may be modified. As a result of adaptive modification of the prefetch distance D, an improved rate of cache hits may be realized.
    Type: Application
    Filed: January 3, 2013
    Publication date: May 21, 2015
    Inventors: Demos Pavlou, Pedro Lopez, Mirem Hyuseinova, Fernando Latorre, Steffen Kosinski, Ralf Goettsche, Varun K. Mohandru
  • METHOD AND APPARATUS FOR A PARTIAL-ADDRESS SELECT-SIGNAL GENERATOR WITH ADDRESS SHIFT
    Publication number: 20130339660
    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing and using a partial-address select-signal generator with address shift.
    Type: Application
    Filed: December 21, 2011
    Publication date: December 19, 2013
    Inventors: Lutz Naethke, Eric Desmarais, Ralf Goettsche