Patents by Inventor Ralf Ludewig
Ralf Ludewig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11860789Abstract: A cache purge simulation system includes a device under test with a cache skip switch. A first cache skip switch includes a configurable state register to indicate whether all of an associated cache is purged upon receipt of a cache purge instruction from a verification system or whether a physical partition that is smaller than the associated cache is purged upon receipt of the cache purge instruction from the verification system. A second cache skip switch includes a configurable start address register comprising a start address that indicates a beginning storage location of a physical partition of an associated cache and a configurable stop address register comprising a stop address that indicates a ending storage location of the physical partition of the associated cache.Type: GrantFiled: March 21, 2022Date of Patent: January 2, 2024Assignee: International Business Machines CorporationInventors: Yvo Thomas Bernard Mulder, Ralf Ludewig, Huiyuan Xing, Ulrich Mayer
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Publication number: 20230297509Abstract: A cache purge simulation system includes a device under test with a cache skip switch. A first cache skip switch includes a configurable state register to indicate whether all of an associated cache is purged upon receipt of a cache purge instruction from a verification system or whether a physical partition that is smaller than the associated cache is purged upon receipt of the cache purge instruction from the verification system. A second cache skip switch includes a configurable start address register comprising a start address that indicates a beginning storage location of a physical partition of an associated cache and a configurable stop address register comprising a stop address that indicates a ending storage location of the physical partition of the associated cache.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Inventors: Yvo Thomas Bernard Mulder, Ralf Ludewig, Huiyuan Xing, Ulrich Mayer
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Patent number: 8868960Abstract: A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.Type: GrantFiled: June 28, 2011Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: Tobias Bergmann, Ralf Ludewig, Tobias Webel, Ulrich Weiss
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Patent number: 8479070Abstract: An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.Type: GrantFiled: June 24, 2010Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Ulrich Baur, Lawrence D. Curley, Ronald J. Frishmuth, Ralf Ludewig, Ching L. Tong, Tobias Webel
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Publication number: 20120151423Abstract: An improved method for performing a formal verification of a property in an electronic circuit design comprises: specifying at least one safety property in the electronic circuit design at a register-transfer level, setting boundaries of a logic cone to a start level according to a configurable structural design criterion, extracting the logic cone from the electronic circuit design based on the at least one specified safety property and the set boundaries, executing a formal verification tool on the logic cone to verify the at least one specified property, extending the boundary of the logic cone according to a configurable structural design criterion and performing the extracting and executing on the new logic cone, if the verification result does not satisfy the at least one safety property.Type: ApplicationFiled: October 28, 2011Publication date: June 14, 2012Applicant: International Business Machines CorporationInventors: Jason R. Baumgartner, Tilman Gloekler, Christoph Jaeschke, Ralf Ludewig
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Publication number: 20120005516Abstract: A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.Type: ApplicationFiled: June 28, 2011Publication date: January 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tobias BERGMANN, Ralf LUDEWIG, Tobias WEBEL, Ulrich WEISS
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Publication number: 20110320898Abstract: An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.Type: ApplicationFiled: June 24, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ulrich Baur, Lawrence D. Curley, Ronald J. Frishmuth, Ralf Ludewig, Ching L. Tong, Tobias Webel
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Patent number: 8055931Abstract: A method is provided for switching between two oscillator signals within an alignment element. In accordance with the method, one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. The method comprises introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected. The method further comprises sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed.Type: GrantFiled: October 6, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Ralf Ludewig, Thuyen Le, Tilman Gloekler, Willm Hinrichs
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Patent number: 7966536Abstract: A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.Type: GrantFiled: April 11, 2008Date of Patent: June 21, 2011Assignee: International Business Machines CorporationInventors: Ralf Ludewig, Walter Niklaus, Dietmar Schmunkamp, Scott Barnett Swaney, Tobias Webel
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Patent number: 7788432Abstract: The various embodiments described herein relate to a system for performing a serial communication between a central control block and a plurality of satellite components within a semiconductor chip. The system comprises at least one logical ring that serially connects the satellite components to the central control block. The system further comprises a centralized timer. The satellite components aid the system in obeying protocols and performing direct accesses to and/or from registers. The logical ring comprises at least one data channel that is provided for transmitting data packets and address packets. Single-envelope transactions are implemented. Errors of the satellite components associated with the single-envelope transactions are reported to the central control block as additional acknowledgement information.Type: GrantFiled: October 2, 2008Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventors: Ralf Ludewig, Thuyen Le, Tobias Webel, Klaus Peter Gungl
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Publication number: 20090259899Abstract: A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.Type: ApplicationFiled: April 11, 2008Publication date: October 15, 2009Inventors: Ralf Ludewig, Walter Niklaus, Dietmar Schmunkamp, Scott Barnett Swaney, Tobias Webel
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Publication number: 20090113094Abstract: The various embodiments described herein relate to a system for performing a serial communication between a central control block and a plurality of satellite components within a semiconductor chip. The system comprises at least one logical ring that serially connects the satellite components to the central control block. The system further comprises a centralized timer. The satellite components aid the system in obeying protocols and performing direct accesses to and/or from registers. The logical ring comprises at least one data channel that is provided for transmitting data packets and address packets. Single-envelope transactions are implemented. Errors of the satellite components associated with the single-envelope transactions are reported to the central control block as additional acknowledgement information.Type: ApplicationFiled: October 2, 2008Publication date: April 30, 2009Applicant: International Business Machines CorporationInventors: Ralf Ludewig, Thuyen Le, Tobias Webel, Klaus Peter Gungl
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Publication number: 20090100283Abstract: A method for switching between two oscillator signals within an alignment element, wherein one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. Said method comprises the steps of: introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected; sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed; sending the virtual stepping signal to the output of the alignment element in the event of a failure in the master signal until a switch to the other oscillator signal as a new master signal is performed or until the first master signal becomes valid again.Type: ApplicationFiled: October 6, 2008Publication date: April 16, 2009Applicant: International Business Machines CorporationInventors: Ralf Ludewig, Thuyen Le, Tilman Gloekler, Willm Hinrichs
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Publication number: 20080276022Abstract: A method to resolve a deadlock in a bus architecture comprising a first and a second single-envelope bus with at least one master and one slave each, where the first and second single-envelope buses are arranged on different sides of an asynchronous boundary and are coupled via a bus bridge, said method comprising the steps of: granting the bus to a first master arranged on a first side of the asynchronous boundary which requests a transaction within a critical time window; monitoring the bus which has been granted for transaction to the first master; stealing silently the bus from the first master if a deadlock condition arises; granting the bus to a second master arranged on a second side of the asynchronous boundary raising the deadlock condition by requesting a second transaction within the critical time window; completing the second transaction to resolve the deadlock scenario; and returning back the bus to the first master to complete the first transaction.Type: ApplicationFiled: April 28, 2008Publication date: November 6, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thuyen Le, Ralf Ludewig