Patents by Inventor Ralf Plieninger

Ralf Plieninger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9601475
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: March 21, 2017
    Assignee: Intel Deutschland GmbH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Publication number: 20160163682
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Application
    Filed: February 11, 2016
    Publication date: June 9, 2016
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Patent number: 9331057
    Abstract: A semiconductor device is disclosed. One embodiment provides a semiconductor chip. The semiconductor chip includes a first electrode of a capacitor. An insulating layer is arranged on top of the first electrode. A second electrode of the capacitor is applied over the insulating layer, wherein the second electrode is made of a conductive layer arranged over the semiconductor chip.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: May 3, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Grit Sommer, Ralf Plieninger
  • Patent number: 9293423
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 22, 2016
    Assignee: Intel Deutschland GmbH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Publication number: 20140332937
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Application
    Filed: July 14, 2014
    Publication date: November 13, 2014
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Patent number: 8779563
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: July 15, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Brandl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Publication number: 20130228904
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Application
    Filed: November 9, 2012
    Publication date: September 5, 2013
    Applicant: INTEL MOBILE COMMUNICATIONS GMBH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Brandl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Patent number: 8309454
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: November 13, 2012
    Assignee: Intel Mobile Communications GmbH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Patent number: 7687895
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also includes an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: March 30, 2010
    Assignee: Infineon Technologies AG
    Inventors: Markus Brunnbauer, Jens Pohl, Klaus Pressel, Thorsten Meyer, Recai Sezi, Stephan Bradl, Ralf Plieninger
  • Publication number: 20090108401
    Abstract: A semiconductor device is disclosed. One embodiment provides a semiconductor chip. The semiconductor chip includes a first electrode of a capacitor. An insulating layer is arranged on top of the first electrode. A second electrode of the capacitor is applied over the insulating layer, wherein the second electrode is made of a conductive layer arranged over the semiconductor chip.
    Type: Application
    Filed: October 26, 2007
    Publication date: April 30, 2009
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thorsten Meyer, Grit Sommer, Ralf Plieninger
  • Publication number: 20080265383
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.
    Type: Application
    Filed: November 14, 2007
    Publication date: October 30, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Markus Brunnbauer, Jens Pohl, Klaus Pressel, Thorsten Meyer, Recai Sezi, Stephan Bradl, Ralf Plieninger
  • Publication number: 20080265421
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Application
    Filed: May 10, 2007
    Publication date: October 30, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger