Abstract: Embodiments relate to tire localization in tire pressure monitoring systems (TPMS). In embodiments, a TPMS includes a wheel unit and a control unit. Each wheel unit collects acceleration data and transmits that data to the control unit for processing. The control unit processes the data and, using additional data received from another vehicle system, for example an antilock braking system (ABS) or electronic stability control (ESC) system, correlates the data in order to localize each wheel unit to a particular wheel of the vehicle. Advantages include increased processing power at the control unit as compared to the wheel unit.

Abstract: Embodiments relate to xMR sensors having very high shape anisotropy. Embodiments also relate to novel structuring processes of xMR stacks to achieve very high shape anisotropies without chemically affecting the performance relevant magnetic field sensitive layer system while also providing comparatively uniform structure widths over a wafer, down to about 100 nm in embodiments. Embodiments can also provide xMR stacks having side walls of the performance relevant free layer system that are smooth and/or of a defined lateral geometry which is important for achieving a homogeneous magnetic behavior over the wafer.

Abstract: The invention provides an amplifier arrangement which is of multistage design. The output transistor in the output stage has a coupling path between its control input and its controlled path. The coupling path comprises a series circuit comprising a Miller compensation capacitance and a resistance with a controllable resistance value. It is thus possible to ensure stable operation of the amplifier regardless of bias and load conditions while simultaneously reducing the quiescent current drawn.

Abstract: A digital/analog converter apparatus (DAC) comprises, for the purpose of converting a digital input signal (D) into an analog output signal (A), a first unit (F1, F2), two digital/analog converters (DAC1, DAC2) and a second unit (K1, K2), which are connected successively in the stated order. From the digital input signal (D), digital intermediate signals (D1, D2) which are within the analog output signal (A) is obtained through linear combination.

Abstract: The invention provides an amplifier arrangement which is of multistage design. The output transistor in the output stage has a coupling path between its control input and its controlled path. The coupling path comprises a series circuit comprising a Miller compensation capacitance and a resistance with a controllable resistance value. It is thus possible to ensure stable operation of the amplifier regardless of bias and load conditions while simultaneously reducing the quiescent current drawn.

Abstract: A digital/analog converter apparatus (DAC) comprises, for the purpose of converting a digital input signal (D) into an analog output signal (A), a first unit (F1, F2), two digital/analog converters (DAC1, DAC2) and a second unit (K1, K2), which are connected successively in the stated order. From the digital input signal (D), digital intermediate signals (D1, D2) which are within the analog output signal (A) is obtained through linear combination.

Abstract: An apparatus converts a digital value including “a” bits into an analog signal and has 2b D/A converters. Here, b is an integer number that is greater than 0. Each of the D/A converters is designed to convert a digital value having “a−b” bits. The digital value that is supplied (for i=1 . . . 2b) to the ith D/A converter for the purpose of D/A conversion corresponds to the “a−b” most significant bits in the sum of the digital value that will be converted by the apparatus and to i−1. The output signal for the apparatus is the mean value for the output signals from the D/A converters. Such an apparatus can be produced such that it can be accommodated easily and efficiently on a semiconductor chip and, irrespective of the details of protocol implementation, permits a completely linear conversion of the digital value being converted into an analog signal.

Abstract: An apparatus converts a digital value including “a” bits into an analog signal and has 2b D/A converters. Here, b is an integer number that is greater than 0. Each of the D/A converters is designed to convert a digital value having “a-b” bits. The digital value that is supplied (for i=1 . . . 2b) to the ith D/A converter for the purpose of D/A conversion corresponds to the “a-b” most significant bits in the sum of the digital value that will be converted by the apparatus and to i−1. The output signal for the apparatus is the mean value for the output signals from the D/A converters. Such an apparatus can be produced such that it can be accommodated easily and efficiently on a semiconductor chip and, irrespective of the details of protocol implementation, permits a completely linear conversion of the digital value being converted into an analog signal.