Patents by Inventor Ralf Rudolf
Ralf Rudolf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230238459Abstract: A semiconductor device includes a semiconductor layer, an electronic element and laterally separated trench isolation structures. The semiconductor layer includes an element region having an inner region, an outer region on opposite sides of the inner region, and a transition region that laterally separates the inner region and the outer region. The electronic element includes a first doped region formed in the inner region and a second doped region formed in the outer region. The trench isolation structures are formed at least in the transition region. Each trench isolation structure extends from a first surface of the semiconductor layer into the semiconductor layer.Type: ApplicationFiled: January 20, 2023Publication date: July 27, 2023Inventors: Lars Müller-Meskamp, Ralf Rudolf, Annett Winzer, Christian Schippel, Thomas Künzig, Dirk Priefert
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Publication number: 20230140348Abstract: A semiconductor device includes a semiconductor layer with an inner portion, an outer portion laterally surrounding the inner portion, and a transition portion laterally surrounding the inner portion and separating the inner portion and the outer portion. A first electric element includes a first doped region formed in the inner portion and a second doped region formed in the outer portion. The first electric element is configured to at least temporarily block a voltage applied between the first doped region and the second doped region. A trench isolation structure extends from a first surface into the semiconductor layer and segments at least one of the inner portion, the transition portion, and the outer portion.Type: ApplicationFiled: October 21, 2022Publication date: May 4, 2023Inventors: Lars Müller-Meskamp, Ralf Rudolf, Dirk Priefert, Annett Winzer, Thomas Künzig, Christian Schippel
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Publication number: 20230075374Abstract: A semiconductor device includes an insulator layer and a semiconductor layer formed on the insulator layer. The semiconductor layer includes a first region of a first conductivity type, a second region of a second conductivity type, and a lightly doped extension region of the first conductivity type separating the first region and the second region along a lateral x-axis. A dielectric structure laterally surrounds the semiconductor layer. At least one of the first region and the lightly doped extension region is formed at a distance to the dielectric structure along a lateral y-axis orthogonal to the x-axis. Along the x-axis and between the second region and the first region, a lateral extension of the semiconductor layer along the y-axis increases with increasing distance to the second region.Type: ApplicationFiled: September 7, 2022Publication date: March 9, 2023Inventor: Ralf Rudolf
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Patent number: 10581429Abstract: An electronic circuit includes: a drive circuit having an output coupled to a control node of a first electronic switch; a switch circuit with second electronic switches, load paths of the second electronic switches being connected in series, and the switch circuit being connected between a first load node of the first electronic switch and a reference node; and a level shifter coupled between a first signal input and an input of the drive circuit and including cascaded level shifter cells. Each level shifter cell includes a signal input and output, and first and second supply nodes. Each level shifter cell is associated with a respective second electronic switch. The first supply node of each level shifter cell is coupled to a first load node of the associated second electronic switch, and the second supply node is coupled to a second load node of the associated second electronic switch.Type: GrantFiled: June 1, 2018Date of Patent: March 3, 2020Assignee: Infineon Technologies Dresden GmbH & Co. KGInventors: Rolf Weis, Ralf Rudolf, Herwig Wappis
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Patent number: 10546920Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. A first semiconductor layer of a second conductivity type is on the semiconductor substrate. A buried semiconductor layer of the second conductivity type is on the first semiconductor layer. A second semiconductor layer of the second conductivity type is on the buried semiconductor layer. A trench extends through each of the second semiconductor layer, the buried semiconductor layer, and the first semiconductor layer, and into the semiconductor substrate. An insulating structure lines walls of the trench. A conductive filling in the trench is electrically coupled to the semiconductor substrate at a bottom of the trench.Type: GrantFiled: February 22, 2018Date of Patent: January 28, 2020Assignee: Infineon Technologies AGInventors: Andreas Meiser, Ralf Rudolf
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Patent number: 10468248Abstract: In various embodiments, a method is provided. The method may include forming a buried electrically charged region at a predefined position in a first layer in such a way that the buried electrically charged region generates an electric field having a lateral inhomogeneous field distribution above the first layer, and forming a second layer above the first layer using the field distribution in such a way that a structure of the second layer correlates with the position of the buried electrically charged region.Type: GrantFiled: April 12, 2017Date of Patent: November 5, 2019Assignee: Infineon Technologies AGInventors: Heiko Aßmann, Felix Braun, Marcus Dankelmann, Stefan Doering, Karsten Friedrich, Udo Goetschkes, Andreas Greiner, Ralf Rudolf, Jens Schneider
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Publication number: 20190312114Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type on the semiconductor substrate, such that a first section of a pn junction is formed between the semiconductor layer and the semiconductor substrate. A trench structure extends through the semiconductor layer into the semiconductor substrate. The trench structure includes an insulation structure and a contact structure. The insulation structure is formed between the semiconductor layer and the contact structure. The contact structure is electrically connected to the semiconductor substrate at a bottom of the trench. A first semiconductor region of the second conductivity type adjoins the insulation structure and extends along the trench structure into a depth range between the first section of the pn junction and the bottom, such that a second section of the pn junction is formed between the first semiconductor region and the semiconductor substrate.Type: ApplicationFiled: April 5, 2019Publication date: October 10, 2019Inventors: Andreas Meiser, Ralf Rudolf
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Publication number: 20180351549Abstract: An electronic circuit includes: a drive circuit having an output coupled to a control node of a first electronic switch; a switch circuit with second electronic switches, load paths of the second electronic switches being connected in series, and the switch circuit being connected between a first load node of the first electronic switch and a reference node; and a level shifter coupled between a first signal input and an input of the drive circuit and including cascaded level shifter cells. Each level shifter cell includes a signal input and output, and first and second supply nodes. Each level shifter cell is associated with a respective second electronic switch. The first supply node of each level shifter cell is coupled to a first load node of the associated second electronic switch, and the second supply node is coupled to a second load node of the associated second electronic switch.Type: ApplicationFiled: June 1, 2018Publication date: December 6, 2018Inventors: Rolf Weis, Ralf Rudolf, Herwig Wappis
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Publication number: 20180240868Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. A first semiconductor layer of a second conductivity type is on the semiconductor substrate. A buried semiconductor layer of the second conductivity type is on the first semiconductor layer. A second semiconductor layer of the second conductivity type is on the buried semiconductor layer. A trench extends through each of the second semiconductor layer, the buried semiconductor layer, and the first semiconductor layer, and into the semiconductor substrate. An insulating structure lines walls of the trench. A conductive filling in the trench is electrically coupled to the semiconductor substrate at a bottom of the trench.Type: ApplicationFiled: February 22, 2018Publication date: August 23, 2018Inventors: Andreas Meiser, Ralf Rudolf
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Patent number: 9899470Abstract: A method of forming a power semiconductor device includes providing a semiconductor layer of a first conductivity type extending to a first side and having a first doping concentration of first dopants providing majority charge carriers of a first electric charge type in the layer, and forming a deep trench isolation including forming a trench which extends from the first side into the semiconductor layer and includes, in a vertical cross-section perpendicular to the first side, a wall, forming a compensation semiconductor region of the first conductivity type at the wall and having a second doping concentration of the first dopants higher than the first doping concentration, and filling the trench with a dielectric material. The amount of first dopants in the compensation semiconductor region is such that a field-effect of fixed charges of the first electric charge type which are trapped in the trench is at least partly compensated.Type: GrantFiled: May 17, 2017Date of Patent: February 20, 2018Assignee: Infineon Technologies Austria AGInventors: Marko Lemke, Knut Stahrenberg, Ralf Rudolf, Rolf Weis
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Publication number: 20170345892Abstract: A method of forming a power semiconductor device includes providing a semiconductor layer of a first conductivity type extending to a first side and having a first doping concentration of first dopants providing majority charge carriers of a first electric charge type in the layer, and forming a deep trench isolation including forming a trench which extends from the first side into the semiconductor layer and includes, in a vertical cross-section perpendicular to the first side, a wall, forming a compensation semiconductor region of the first conductivity type at the wall and having a second doping concentration of the first dopants higher than the first doping concentration, and filling the trench with a dielectric material. The amount of first dopants in the compensation semiconductor region is such that a field-effect of fixed charges of the first electric charge type which are trapped in the trench is at least partly compensated.Type: ApplicationFiled: May 17, 2017Publication date: November 30, 2017Inventors: Marko Lemke, Knut Stahrenberg, Ralf Rudolf, Rolf Weis
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Publication number: 20170294299Abstract: In various embodiments, a method is provided. The method may include forming a buried electrically charged region at a predefined position in a first layer in such a way that the buried electrically charged region generates an electric field having a lateral inhomogeneous field distribution above the first layer, and forming a second layer above the first layer using the field distribution in such a way that a structure of the second layer correlates with the position of the buried electrically charged region.Type: ApplicationFiled: April 12, 2017Publication date: October 12, 2017Inventors: Heiko Assmann, Felix Braun, Marcus Dankelmann, Stefan Doering, Karsten Friedrich, Udo Goetschkes, Andreas Greiner, Ralf Rudolf, Jens Schneider
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Publication number: 20170040317Abstract: A semiconductor device includes a semiconductor substrate having a first side. At least a first doping region is formed in the semiconductor substrate. The first doping region has a laterally varying doping dosage and/or a laterally varying implantation depth.Type: ApplicationFiled: August 2, 2016Publication date: February 9, 2017Inventors: Stefan Tegen, Martin Bartels, Marko Lemke, Ralf Rudolf, Rolf Weis
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Publication number: 20160343848Abstract: A Transistor arrangement in a semiconductor body comprises a power transistor with at least two transistor cells, each transistor cell arranged in a semiconductor fin of the semiconductor body and with a voltage limiting device with at least two device cells. Each device cell is arranged adjacent a transistor cell in the semiconductor fin of the respective transistor cell and the voltage limiting device is separated from the power transistor by a dielectric layer.Type: ApplicationFiled: May 18, 2016Publication date: November 24, 2016Inventors: Martin Bartels, Marko Lemke, Ralf Rudolf, Stefan Tegen, Rolf Weis
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Patent number: 9406550Abstract: A method for forming an insulation structure in a semiconductor body includes forming a trench extending from a first surface into a semiconductor body, the trench having a first width in a horizontal direction of the semiconductor body, and forming a void spaced apart from the first surface in a vertical direction of the semiconductor body, the void having a second width in a horizontal direction that is greater than the first width, wherein the trench and the void are arranged adjacent to each other in a vertical direction.Type: GrantFiled: October 31, 2013Date of Patent: August 2, 2016Assignee: Infineon Technologies Austria AGInventors: Marko Lemke, Rolf Weis, Ralf Rudolf
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Publication number: 20150115396Abstract: A method for forming an insulation structure in a semiconductor body includes forming a trench extending from a first surface into a semiconductor body, the trench having a first width in a horizontal direction of the semiconductor body, and forming a void spaced apart from the first surface in a vertical direction of the semiconductor body, the void having a second width in a horizontal direction that is greater than the first width, wherein the trench and the void are arranged adjacent to each other in a vertical direction.Type: ApplicationFiled: October 31, 2013Publication date: April 30, 2015Inventors: Marko Lemke, Rolf Weis, Ralf Rudolf
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Patent number: 9000520Abstract: A semiconductor device includes an electrode arranged on a main surface of a semiconductor body and an insulating structure insulating the electrode from the semiconductor body. The insulating structure includes in a vertical cross-section a gate dielectric portion forming a first horizontal interface at least with a drift region of the device and having a first maximum vertical extension between the first horizontal interface and the electrode, and a field dielectric portion forming with the drift region second, third and fourth horizontal interfaces. The second through fourth horizontal interfaces are arranged below the main surface. The third horizontal interface is arranged between the second and fourth horizontal interfaces. A second maximum vertical extension is larger than the first maximum vertical extension and a third maximum vertical extension is larger than the second maximum vertical extension. The electrode only partially overlaps the third horizontal interface.Type: GrantFiled: February 11, 2014Date of Patent: April 7, 2015Assignee: Infineon Technologies Dresden GmbHInventors: Marc Strasser, Karl-Heinz Gebhardt, Ralf Rudolf, Lincoln O'Riain
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Publication number: 20140159154Abstract: A semiconductor device includes an electrode arranged on a main surface of a semiconductor body and an insulating structure insulating the electrode from the semiconductor body. The insulating structure includes in a vertical cross-section a gate dielectric portion forming a first horizontal interface at least with a drift region of the device and having a first maximum vertical extension between the first horizontal interface and the electrode, and a field dielectric portion forming with the drift region second, third and fourth horizontal interfaces. The second through fourth horizontal interfaces are arranged below the main surface. The third horizontal interface is arranged between the second and fourth horizontal interfaces. A second maximum vertical extension is larger than the first maximum vertical extension and a third maximum vertical extension is larger than the second maximum vertical extension. The electrode only partially overlaps the third horizontal interface.Type: ApplicationFiled: February 11, 2014Publication date: June 12, 2014Inventors: Marc Strasser, Karl-Heinz Gebhardt, Ralf Rudolf, Lincoln O'Riain
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Patent number: 8686505Abstract: A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.Type: GrantFiled: July 27, 2012Date of Patent: April 1, 2014Assignee: Infineon Technologies Dresden GmbHInventors: Marc Strasser, Karl-Heinz Gebhardt, Ralf Rudolf, Lincoln O'Riain
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Publication number: 20140027848Abstract: A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.Type: ApplicationFiled: July 27, 2012Publication date: January 30, 2014Applicant: INFINEON TECHNOLOGIES DRESDEN GMBHInventors: Marc Strasser, Karl-Heinz Gebhardt, Ralf Rudolf, Lincoln O'Riain