Abstract: An integrated circuit includes a semiconductor layer with a first portion in a first device region and a second portion in a second device region. A galvanic isolation structure is formed between the first portion and the second portion of the semiconductor layer. A capacitive coupling element is formed on a first surface of the semiconductor layer. The capacitive coupling element includes a first lower electrode in the first device region and a capacitor dielectric separating the first lower electrode from a top electrode spanning across the galvanic isolation structure. The first lower electrode is signal-connected to a first circuit element in the first device region. The top electrode is operatively connected to a second circuit element in the second device region.

Abstract: A semiconductor device includes a semiconductor layer, an electronic element and laterally separated trench isolation structures. The semiconductor layer includes an element region having an inner region, an outer region on opposite sides of the inner region, and a transition region that laterally separates the inner region and the outer region. The electronic element includes a first doped region formed in the inner region and a second doped region formed in the outer region. The trench isolation structures are formed at least in the transition region. Each trench isolation structure extends from a first surface of the semiconductor layer into the semiconductor layer.

Abstract: A lateral high voltage semiconductor device includes a semiconductor substrate with a frontside and a semiconductor element. The semiconductor element includes: a first semiconductor region of a first conductivity type formed within the semiconductor substrate; a second semiconductor region formed within the semiconductor substrate and spaced apart from the first semiconductor region in a first lateral direction parallel to the frontside; and an extension region adjoining the second semiconductor region. The semiconductor device is configured to control a load current between the first and second semiconductor regions. The extension region extends along the frontside of the semiconductor substrate and includes at least one mesa protruding at the frontside of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor layer with an inner portion, an outer portion laterally surrounding the inner portion, and a transition portion laterally surrounding the inner portion and separating the inner portion and the outer portion. A first electric element includes a first doped region formed in the inner portion and a second doped region formed in the outer portion. The first electric element is configured to at least temporarily block a voltage applied between the first doped region and the second doped region. A trench isolation structure extends from a first surface into the semiconductor layer and segments at least one of the inner portion, the transition portion, and the outer portion.

Abstract: A semiconductor device includes a buried semiconductor substrate layer interposed between a lower semiconductor substrate layer of a different conductivity type and an upper semiconductor substrate layer. A first isolation trench extends through the upper semiconductor substrate layer and the buried semiconductor substrate layer into the lower semiconductor substrate layer, includes a first insulating material formed at an inner sidewall of the first isolation trench, and is filled with a first electrically conductive material. A second isolation trench extends through the upper semiconductor substrate layer and the buried semiconductor substrate layer into the lower semiconductor substrate layer, includes a second insulating material formed at an inner sidewall and a bottom of the second isolation trench, and is either devoid of a second electrically conductive material or only a minor portion of the second isolation trench is filled with the second electrically conductive material.

Abstract: A semiconductor device includes an insulator layer and a semiconductor layer formed on the insulator layer. The semiconductor layer includes a first region of a first conductivity type, a second region of a second conductivity type, and a lightly doped extension region of the first conductivity type separating the first region and the second region along a lateral x-axis. A dielectric structure laterally surrounds the semiconductor layer. At least one of the first region and the lightly doped extension region is formed at a distance to the dielectric structure along a lateral y-axis orthogonal to the x-axis. Along the x-axis and between the second region and the first region, a lateral extension of the semiconductor layer along the y-axis increases with increasing distance to the second region.

Abstract: A FET includes a transistor cell which includes: a source region at a first surface of a semiconductor substrate; a drain region spaced along a first lateral direction from the source region; a trench gate structure arranged, along the first lateral direction, between the source and drain regions; a body region adjoining the trench gate structure; and a body contact region. At least one of the following conditions is satisfied: a first vertical distance from the body contact region bottom side to a vertical reference level at the first surface is larger than a second vertical distance from the source region bottom side to the vertical reference level; and a first lateral distance from an edge of the body contact region to a lateral reference level at the drain region is smaller than a second lateral distance from an edge of the source region to the lateral reference level.

Abstract: A lateral high voltage semiconductor device includes a semiconductor substrate with a frontside and a semiconductor element. The semiconductor element includes: a first semiconductor region of a first conductivity type formed within the semiconductor substrate; a second semiconductor region formed within the semiconductor substrate and spaced apart from the first semiconductor region in a first lateral direction parallel to the frontside; and an extension region adjoining the second semiconductor region. The semiconductor device is configured to control a load current between the first and second semiconductor regions. The extension region extends along the frontside of the semiconductor substrate and includes at least one mesa protruding at the frontside of the semiconductor substrate.

Abstract: A semiconductor device includes: a silicon layer having an electrically insulated backside and a thickness in a range of 10 ?m to 200 ?m between a frontside of the silicon layer and the electrically insulated backside; a high voltage region and a low voltage region formed in the silicon layer and laterally spaced apart from one another; and a first field plate structure extending from the frontside into the silicon layer. The first field plate structure includes a field plate laterally separated from the silicon layer by a dielectric material and/or a pn junction.

Abstract: A gate driver circuit includes a low side part and a high side part. The low side part outputs a first gate drive signal between a first gate output and a first reference potential. The high side part generates a high side data signal and outputs a second gate drive signal between a second gate output and a second reference potential. A p-channel junction field effect transistor structure passes the high side data signal to the low side part.

Abstract: A semiconductor device includes: a silicon layer having a frontside and an electrically insulated backside; a first trench extending through the silicon layer from the frontside to the electrically insulated backside and laterally isolating a first region of the silicon layer; an electrically conductive material in the first trench; a dielectric material separating the electrically conductive material from silicon material of the silicon layer; and a plurality of silicon plugs laterally surrounded by the dielectric material and dividing the electrically conductive material into a plurality of separate segments in the first trench. Additional embodiments of semiconductor devices and methods for manufacturing the semiconductor devices are also described.

Abstract: A semiconductor device includes a semiconductor layer, an electronic element and laterally separated trench isolation structures. The semiconductor layer includes an element region having an inner region, an outer region on opposite sides of the inner region, and a transition region that laterally separates the inner region and the outer region. The electronic element includes a first doped region formed in the inner region and a second doped region formed in the outer region. The trench isolation structures are formed at least in the transition region. Each trench isolation structure extends from a first surface of the semiconductor layer into the semiconductor layer.

Abstract: A semiconductor device includes a semiconductor layer with an inner portion, an outer portion laterally surrounding the inner portion, and a transition portion laterally surrounding the inner portion and separating the inner portion and the outer portion. A first electric element includes a first doped region formed in the inner portion and a second doped region formed in the outer portion. The first electric element is configured to at least temporarily block a voltage applied between the first doped region and the second doped region. A trench isolation structure extends from a first surface into the semiconductor layer and segments at least one of the inner portion, the transition portion, and the outer portion.

Abstract: A semiconductor device includes an insulator layer and a semiconductor layer formed on the insulator layer. The semiconductor layer includes a first region of a first conductivity type, a second region of a second conductivity type, and a lightly doped extension region of the first conductivity type separating the first region and the second region along a lateral x-axis. A dielectric structure laterally surrounds the semiconductor layer. At least one of the first region and the lightly doped extension region is formed at a distance to the dielectric structure along a lateral y-axis orthogonal to the x-axis. Along the x-axis and between the second region and the first region, a lateral extension of the semiconductor layer along the y-axis increases with increasing distance to the second region.

Abstract: An electronic circuit includes: a drive circuit having an output coupled to a control node of a first electronic switch; a switch circuit with second electronic switches, load paths of the second electronic switches being connected in series, and the switch circuit being connected between a first load node of the first electronic switch and a reference node; and a level shifter coupled between a first signal input and an input of the drive circuit and including cascaded level shifter cells. Each level shifter cell includes a signal input and output, and first and second supply nodes. Each level shifter cell is associated with a respective second electronic switch. The first supply node of each level shifter cell is coupled to a first load node of the associated second electronic switch, and the second supply node is coupled to a second load node of the associated second electronic switch.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. A first semiconductor layer of a second conductivity type is on the semiconductor substrate. A buried semiconductor layer of the second conductivity type is on the first semiconductor layer. A second semiconductor layer of the second conductivity type is on the buried semiconductor layer. A trench extends through each of the second semiconductor layer, the buried semiconductor layer, and the first semiconductor layer, and into the semiconductor substrate. An insulating structure lines walls of the trench. A conductive filling in the trench is electrically coupled to the semiconductor substrate at a bottom of the trench.

Abstract: In various embodiments, a method is provided. The method may include forming a buried electrically charged region at a predefined position in a first layer in such a way that the buried electrically charged region generates an electric field having a lateral inhomogeneous field distribution above the first layer, and forming a second layer above the first layer using the field distribution in such a way that a structure of the second layer correlates with the position of the buried electrically charged region.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type on the semiconductor substrate, such that a first section of a pn junction is formed between the semiconductor layer and the semiconductor substrate. A trench structure extends through the semiconductor layer into the semiconductor substrate. The trench structure includes an insulation structure and a contact structure. The insulation structure is formed between the semiconductor layer and the contact structure. The contact structure is electrically connected to the semiconductor substrate at a bottom of the trench. A first semiconductor region of the second conductivity type adjoins the insulation structure and extends along the trench structure into a depth range between the first section of the pn junction and the bottom, such that a second section of the pn junction is formed between the first semiconductor region and the semiconductor substrate.

Abstract: An electronic circuit includes: a drive circuit having an output coupled to a control node of a first electronic switch; a switch circuit with second electronic switches, load paths of the second electronic switches being connected in series, and the switch circuit being connected between a first load node of the first electronic switch and a reference node; and a level shifter coupled between a first signal input and an input of the drive circuit and including cascaded level shifter cells. Each level shifter cell includes a signal input and output, and first and second supply nodes. Each level shifter cell is associated with a respective second electronic switch. The first supply node of each level shifter cell is coupled to a first load node of the associated second electronic switch, and the second supply node is coupled to a second load node of the associated second electronic switch.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. A first semiconductor layer of a second conductivity type is on the semiconductor substrate. A buried semiconductor layer of the second conductivity type is on the first semiconductor layer. A second semiconductor layer of the second conductivity type is on the buried semiconductor layer. A trench extends through each of the second semiconductor layer, the buried semiconductor layer, and the first semiconductor layer, and into the semiconductor substrate. An insulating structure lines walls of the trench. A conductive filling in the trench is electrically coupled to the semiconductor substrate at a bottom of the trench.