Abstract: A gas-sensitive field-effect transistor may be formed from a substrate with a gas-sensitive layer and a transistor processed separately and then assembled. The substrate may be patterned to form spacers by which the height of an air gap between the transistor and the sensitive layer may be adjustable to a relatively precise degree. Formation of the spacers can be achieved by patterning the substrate using material-removal techniques. The height of the spacers may be adjusted in the layer thickness of the gas-sensitive layer and for the transistor fabricated using a CMOS process. Suitable techniques for producing recesses between the spacers include, for example, polishing, cutting, sandblasting, lithographic dry etching, or wet-chemical etching. Suitable materials for the substrate may include, for example, glass, ceramic, aluminum oxide, silicon, or a dimensionally stable polymer.

Abstract: The invention relates to a method for coating surfaces of metal objects, especially as a pre-treatment for cold deformation or as a pre-treatment for a metal-rubber compound or to adjust friction coefficients in connection elements, used in connection elements such as screws for screwing purposes. The invention is characterised in that the optionally, already pre-coated metal objects are coated with a composition containing an aqueous, acidic phosphate, said composition containing 8-50 g/L phosphate as PO4, 0.5-30 g/L zinc ions, 0-5 g/L manganese ions, 0-8 g/L calcium ions, 0-5 g/L magnesium ions, whereby at least 0.1 g/L of calcium or/and magnesium ions are provided, 0.1-5 g/L nitroguanidine, 0.1-8 g/L chlorate or/and peroxide ions and 0-16 g/L complex fluoride (MeF4 or/and MeF6) of Me=B, Si, Ti, Hf or/and Zr and 0-5 g/L fluoride ions, whereby the total amount of complex fluoride and fluoride ions ranges from 0.1-18 g/L.

Abstract: In a method for initializing at least one electronic circuit unit of an electric circuit, a supply voltage is applied to a power supply connection unit of the electronic circuit in order to supply electrical power to the electronic circuit unit. A reference signal is applied to the electronic circuit unit via a reference signal connection unit. A blocking unit connected to the reference signal connection unit blocks the electronic circuit unit until the reference signal is supplied. An input signal to the electronic circuit unit is supplied via an input signal connection unit of the electronic circuit and an output signal is output by an output signal connection unit of the electronic circuit. The output signal is dependent on the input signal and the reference signal supplied to the electronic circuit unit.

Abstract: The present invention provides an apparatus for signaling that a predetermined time value has elapsed, having a device for acquiring and storing the amplitude value of a clock signal at an acquisition instant in the temporal profile of the clock signal. A device is provided for continuously comparing the acquired and stored amplitude value of the clock signal with an instantaneous amplitude value of the clock signal and for outputting a comparison signal which has a first logic state if the instantaneous amplitude value of the clock signal is less than the stored amplitude value and has a second logic state if the instantaneous amplitude value of the clock signal is greater than the stored amplitude value.

Abstract: The invention relates to a RAM store having a shared SA structure, in which sense amplifiers (SA) arranged in SA strips (10) between two respective adjacent cell blocks are used by a plurality of bit line pairs (21, 22; 21–24) from the adjacent cell blocks and the bit line pairs (21, 22; 21–24) have respective charge equalization circuits individually associated with them for the purpose of performing charge equalization between the bit line halves of the bit line pairs (21, 22; 21–24) in a precharge phase, where a shorting transistor (30) is provided which, when prompted by a control signal (EQLx), connects the bit line halves (BLT, BLC) of the bit line pairs (21, 22; 21–24) which are in the precharge phase to one another.

Abstract: An integrated memory contains a memory cell array, which has word lines and bit lines, and a read/write amplifier, which is connected to the bit lines for the assessing and amplifying data signals. A voltage generator circuit generates a voltage supply for application to the read/write amplifier. A potential difference is applied to the read/write amplifier using different supply potentials. The voltage generator circuit increases the potential difference applied to the read/write amplifier for a limited period of time during an assessment and amplification operation of the read/write amplifier. Charge-dependent control is implemented in the voltage generator circuit. An assessment and amplification operation can be carried out at a comparatively high switching speed and a low power consumption is possible.

Abstract: An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.

Abstract: An integrated circuit includes a programming circuit (10) for generating programming signals (PS1, . . . , PS4) with a first input terminal (E1) for applying a control voltage (ES), a second input terminal (E2) for applying a reference voltage (Vref), a storage circuit (30) with programmable switches (35, . . . , 38) and output terminals (A1, . . . , A4). The programming circuit in each case generates a programming signal (PS1, . . . , PS4) when the control voltage (ES) exceeds a predefined threshold voltage formed from the reference voltage. The number of programming signals (PS1, . . . , PS4) is dependent on the magnitude of the threshold voltage exceeded by the control voltage (ES). The programming signals are used for programming the programmable switches (35, . . . , 38). The programming state of the programmable switches can be read out via the output terminals (A1, . . . , A4) of the integrated circuit.

Abstract: The invention relates to an aqueous concentrate which is stable with respect to freezing and defrosting and which contains at least one water-soluble or water-dispersible copper compound and, optionally, also a water-soluble or water-dispersible tin compound for use in a diluted state as a bath for the currentless copper plating or bronze plating of objects, especially metal objects such as iron or steel wires, characterised in that it contains at least one complexed water-soluble or water-dispersed copper compound. The invention also relates to an aqueous bath which contains at least one aqueous or water-dispersible copper compound and, optionally, a water-soluble or water-dispersible tin compound for the currentless copper plating of objects in addition to at least one brightening agent and which has an adjusted pH value of less than 2.5. The invention also relates to a method for currentless copper plating or bronze plating of an object, especially a metallic object.

Abstract: An integrated semiconductor memory includes a DRAM memory, in which primary sense amplifiers (SA) are coupled to a bit line (BL) of a respective cell block and can be connected to a common local data line (LDQ) by means of a respective assigned CSL switch in response to a CSL signal and in which an MDQ/LDQ switch arrangement connects a main data line (MDQ) to the local data line (LDQ) of a respective cell block in response to an MDQ/LDQ switch signal. In the case of the semiconductor memory, a control input of each CSL switch is connected to an AND element, which ANDs the CSL signal with the MDQ/LDQ switch signal and thereby activates the CSL switches only in cell blocks in which a word line has been activated.

Abstract: An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T1) and a second branch including a charge pump (10) and a second controllable resistance (T2) are connected between the input terminal (IN) and the output terminal (A). A control circuit (20) alters the resistance values of the first and second controllable resistances (T1, T2) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.

Abstract: In a driver circuit having a plurality of drivers for driving signals in parallel, the drivers are each connected to an input signal line for receiving a respective input signal and to an output signal line for outputting a respective driven output signal. An output signal line of one of the drivers may be connected, via a switch or switching means, to an output signal line of another of the drivers. A control circuit is connected to one of the drivers and is used to drive the switch or switching means in such a manner that the switching means can be activated, for charge equalization, by the control circuit following a driving operation in one of the drivers. A respective associated memory circuit, by which an associated logic circuit for driving one of the switch or switching means is connected to the relevant output signal line, is connected to the respective output signal line. Overall power consumption of the driver circuit can be minimized.

Abstract: Integrated semiconductor circuits, in particular, dynamic random access memories include a multiplicity of generator circuits for generating internal voltage levels from an externally applied supply voltage. During testing, the internal voltage levels are altered by the output voltage generated at the output of the generator circuit being adapted to an externally applied test voltage. If the test voltage is outside a tolerance range, the semiconductor circuit maybe destroyed. A protection circuit connected in parallel with the generator circuit limits the output voltage.

Abstract: An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input terminal for applying an input signal. The current pulse circuit is connected to an output terminal via an interconnect for carrying a current. In the test operating state, the current pulse circuit generates at least one first current pulse with a first, predetermined time duration in a first test cycle and at least one second current pulse with a second, unknown time duration in a subsequent second test cycle. In addition to a first current flowing on the interconnect in the normal operating state, a second current flows on the interconnect during the first test cycle and a third current flows during the second test cycle in the test operating state.

Abstract: An integrated circuit includes a circuit component, a first control circuit and a switchable resistance network. An input voltage is fed to the circuit component on the input side. A control signal generated by the first control circuit is fed to the control terminal of the circuit component. With the switchable resistance network, the first resistance or the second resistance is connected between an output terminal of the circuit component and the output terminal of the integrated circuit to generate a voltage drop between the input side and the output terminal of the circuit component. The integrated circuit makes it possible to generate a current at the output terminal of the circuit component in a manner dependent on the control signal and the voltage dropped between the input side and the output terminal of the circuit component. Families of characteristic curves of transistors of an integrated circuit are determined by the integrated circuit.

Abstract: An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying an input voltage, which is generated internally from an externally applied supply voltage by a voltage generator circuit. The current generator circuit is connected to an output terminal via an interconnect. A first current flows on the interconnect in a test operating state of the integrated circuit. The current generator circuit generates a first partial current in a first test cycle of a test operating state and a second partial current in a subsequent second test cycle. The partial currents are each superposed on the first current on the interconnect. Consequently, three currents occur at the output terminal during the test operating state. The internally generated input voltage of the current generator circuit is determined from the three currents and the reference voltage.

Abstract: A field effect semiconductor comprises a semiconductor layer having a surface, a first and a second semiconductor region in the semiconductor layer, which are arranged next to one another at the surface of the semiconductor layer, an insulating layer between the first semiconductor region and the second semiconductor region, a semiconductor strip on the surface of the semiconductor layer, which semiconductor strip overlaps the first semiconductor region and the second semiconductor region and adjoins these. A gate overlaps the semiconductor strip at least in the region of the insulating layer. A gate dielectric insulates the gate from the semiconductor strip the first semiconductor region and the second semiconductor region. The semiconductor strip and the gate being formed such that the semiconductor strip is electrically insulating at a first predetermined gate voltage and is electrically conductive at a second predetermined gate voltagero.

Abstract: An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.

Abstract: A voltage generator arrangement supplies a largely constant output voltage with a high current driver capability. A bandgap reference circuit drives a voltage generator on the output side, if necessary via an impedance converter. The bandgap reference circuit and the impedance converter on the one hand, and the voltage generator on the other hand, are connected to different reference ground potential lines. The voltage generator on the output side is preceded by a correction circuit, which corrects for the voltage drop on that reference ground potential line to which the output-side voltage generator is connected. The voltage generator arrangement is suitable for a greater integration density.

Abstract: An integrated circuit includes a programming circuit (10) for generating programming signals (PS1, . . . , PS4) with a first input terminal (E1) for applying a control voltage (ES), a second input terminal (E2) for applying a reference voltage (Vref), a storage circuit (30) with programmable switches (35, . . . , 38) and output terminals (A1, . . . , A4). The programming circuit in each case generates a programming signal (PS1, . . . , PS4) when the control voltage (ES) exceeds a predefined threshold voltage formed from the reference voltage. The number of programming signals (PS1, . . . , PS4) is dependent on the magnitude of the threshold voltage exceeded by the control voltage (ES). The programming signals are used for programming the programmable switches (35, . . . , 38). The programming state of the programmable switches can be read out via the output terminals (A1, . . . , A4) of the integrated circuit.