Patents by Inventor Ralf Winkelmann
Ralf Winkelmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180046743Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.Type: ApplicationFiled: October 26, 2017Publication date: February 15, 2018Inventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
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Publication number: 20180046742Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.Type: ApplicationFiled: October 26, 2017Publication date: February 15, 2018Inventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
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Publication number: 20170344679Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.Type: ApplicationFiled: October 14, 2016Publication date: November 30, 2017Inventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
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Publication number: 20170344684Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.Type: ApplicationFiled: May 27, 2016Publication date: November 30, 2017Inventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
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Publication number: 20170220439Abstract: Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.Type: ApplicationFiled: June 29, 2016Publication date: August 3, 2017Inventors: Christian Habermann, Gerrit Koch, Martin Recktenwald, Ralf Winkelmann
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Publication number: 20170220437Abstract: Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.Type: ApplicationFiled: January 29, 2016Publication date: August 3, 2017Inventors: Christian Habermann, Gerrit Koch, Martin Recktenwald, Ralf Winkelmann
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Publication number: 20160132417Abstract: Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor caches, the graph-based coherency verification tool using trace files as input for verifying memory ordering rules of a given processor architecture for accesses to the caches, wherein nodes in a graph represent memory accesses and edges represent dependencies between them. The verifying includes (i) providing a specification of a test case for a self-checking tool, the test case comprising a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files with the self-checking tool for the graph-based coherency verification tool by producing permutations of trace events, which are defined by the sequence of statements of the test case.Type: ApplicationFiled: November 2, 2015Publication date: May 12, 2016Inventors: Thomas P. GROSSER, Gerrit KOCH, Ralf WINKELMANN
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Patent number: 9075732Abstract: Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.Type: GrantFiled: June 14, 2011Date of Patent: July 7, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christian Habermann, Martin Recktenwald, Hans-Werner Tast, Ralf Winkelmann
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Patent number: 8856444Abstract: Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.Type: GrantFiled: April 28, 2012Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventors: Christian Habermann, Martin Recktenwald, Hans-Werner Tast, Ralf Winkelmann
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Patent number: 8751749Abstract: Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.Type: GrantFiled: June 14, 2011Date of Patent: June 10, 2014Assignee: International Business Machines CorporationInventors: Christian Habermann, Martin Recktenwald, Hans-Werner Tast, Ralf Winkelmann
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Patent number: 8589735Abstract: A mechanism for verifying order of entities being processed by a device under test (DUT) is provided. The mechanism includes arranging the entities into a temporal order, and encoding the entities to maintain the temporal order of the entities and produce encoded entities with each being a random value. The encoded entities each have a one-to-one mapping to their corresponding one of the entities in the temporal order. The encoded entities are input into the DUT to verify its output, and responsive to detecting an error in the output corresponding to one encoded entity, the one encoded entity is decoded into a current decoded error entity. It is determined which is lower in the temporal order between the current decoded error entity and a previous decoded error entity. Responsive to the current decoded error entity being lower than the previous decoded error entity, the current decoded error entity is stored.Type: GrantFiled: May 16, 2011Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Clinton E. Bubb, Chaitanya Kancherla, Roopesh A. Matayambath, Ralf Winkelmann
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Patent number: 8495452Abstract: Handling corrupted background data in an out of order processing environment. Modified data is stored on a byte of a word having at least one byte of background data. A byte valid vector and a byte store bit are added to the word. Parity checking is done on the word. If the word does not contain corrupted background date, the word is propagated to the next level of cache. If the word contains corrupted background data, a copy of the word is fetched from a next level of cache that is ECC protected, the byte having the modified data is extracted from the word and swapped for the corresponding byte in the word copy. The word copy is then written into the next level of cache that is ECC protected.Type: GrantFiled: February 10, 2011Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Michael Fee, Christian Habermann, Christian Jacobi, Diana L. Orf, Martin Recktenwald, Hans-Werner Tast, Ralf Winkelmann
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Publication number: 20120297250Abstract: A mechanism for verifying order of entities being processed by a device under test (DUT) is provided. The mechanism includes arranging the entities into a temporal order, and encoding the entities to maintain the temporal order of the entities and produce encoded entities with each being a random value. The encoded entities each have a one-to-one mapping to their corresponding one of the entities in the temporal order. The encoded entities are input into the DUT to verify its output, and responsive to detecting an error in the output corresponding to one encoded entity, the one encoded entity is decoded into a current decoded error entity. It is determined which is lower in the temporal order between the current decoded error entity and a previous decoded error entity. Responsive to the current decoded error entity being lower than the previous decoded error entity, the current decoded error entity is stored.Type: ApplicationFiled: May 16, 2011Publication date: November 22, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Chaitanya Kancherla, Roopesh A. Matayambath, Ralf Winkelmann
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Patent number: 8302043Abstract: A method and system for verifying a logic circuit design using dynamic clock gating is disclosed. The method comprises choosing at least one master seed to determine initial values as initialization for said logic circuit and/or stimuli data for at least one interface of said logic circuit, choosing at least two different dynamic clock gating configurations for every chosen master seed, executing a functional simulation with said logic circuit for every chosen dynamic clock gating configuration by using said determined initialization and/or stimuli data based on a corresponding master seed, comparing simulation results of functional simulations against each other executed with said logic circuit for at least two different chosen dynamic clock gating configurations, and reporting an error if said at least two simulation results are not identical.Type: GrantFiled: September 7, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Christian Habermann, Christian Jacobi, Matthias Pflanz, Hans-Werner Tast, Ralf Winkelmann
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Publication number: 20120215983Abstract: Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.Type: ApplicationFiled: April 28, 2012Publication date: August 23, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christian Habermann, Martin Recktenwald, Hans-Werner Tast, Ralf Winkelmann
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Publication number: 20120210188Abstract: Handling corrupted background data in an out of order processing environment. Modified data is stored on a byte of a word having at least one byte of background data. A byte valid vector and a byte store bit are added to the word. Parity checking is done on the word. If the word does not contain corrupted background date, the word is propagated to the next level of cache. If the word contains corrupted background data, a copy of the word is fetched from a next level of cache that is ECC protected, the byte having the modified data is extracted from the word and swapped for the corresponding byte in the word copy. The word copy is then written into the next level of cache that is ECC protected.Type: ApplicationFiled: February 10, 2011Publication date: August 16, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Fee, Christian Habermann, Christian Jacobi, Diana L. Orf, Martin Recktenwald, Hans-Werner Tast, Ralf Winkelmann
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Patent number: 8108197Abstract: A coherency algorithm for a multi processor environment to run on a single processor model is verified by: generating a reference model reflecting a private cache hierarchy of a single processor within the multi processor environment, stimulating the private cache hierarchy with simulated requests and/or cross invalidations from a core side and/or from a nest side, and augmenting all data available in the private cache hierarchy with two construction dates and two expiration dates, which are set based on interface events. Multi processor coherency is not observed if the cache hierarchy ever returns data to the processor with an expiration date that is older than the latest construction date of all data used before. Further, a single processor model and a computer program product can be employed to execute the method.Type: GrantFiled: December 4, 2008Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: Christian Habermann, Ralf Winkelmann, Hans-Werner Tast, Christian Jacobi
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Publication number: 20110307666Abstract: Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.Type: ApplicationFiled: June 14, 2011Publication date: December 15, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christian Habermann, Martin Recktenwald, Hans-Werner Tast, Ralf Winkelmann
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Patent number: 8015451Abstract: Controlling an unreliable data transfer in a data channel from a transmitting unit to a receiving unit. A bypass mode or a buffer mode is activated depending on the error rate in the data channel. If bypass mode is selected, data packets are directly transferred in probation from the transmitting unit to the receiving unit by a bypass line. The data packets are error checked after the data transfer. If buffer mode is selected, data is transfer from the transmitting unit to the receiving unit by a buffer line via an error detecting and correcting unit and a buffer unit. The errors are detected and corrected during the data transfer.Type: GrantFiled: January 20, 2009Date of Patent: September 6, 2011Assignee: International Business Machines CorporationInventors: Christian Habermann, Christian Jacobi, Matthias Pflanz, Hans-Werner Tast, Ralf Winkelmann
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Publication number: 20110066988Abstract: A method and system for verifying a logic circuit design using dynamic clock gating is disclosed. The method comprises choosing at least one master seed to determine initial values as initialization for said logic circuit and/or stimuli data for at least one interface of said logic circuit, choosing at least two different dynamic clock gating configurations for every chosen master seed, executing a functional simulation with said logic circuit for every chosen dynamic clock gating configuration by using said determined initialization and/or stimuli data based on a corresponding master seed, comparing simulation results of functional simulations against each other executed with said logic circuit for at least two different chosen dynamic clock gating configurations, and reporting an error if said at least two simulation results are not identical.Type: ApplicationFiled: September 7, 2010Publication date: March 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christian Habermann, Christian Jacobi, Matthias Pflanz, Hans-Werner Tast, Ralf Winkelmann