Patents by Inventor Rallabandi V Lakshmi ANNAPURNA

Rallabandi V Lakshmi ANNAPURNA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock recovery and cable diagnostics for ethernet phy
    Patent number: 11595064
    Abstract: A receiver circuit includes an analog-to-digital converter (ADC), a decision feedback equalizer (DFE), a slicer, and a timing error detector (TED). The DFE is coupled to the ADC, and includes a first tap and a second tap. The slicer is coupled to the DFE. The TED is coupled to the slicer. The TED is configured to initialize timing of a sampling clock provided to the ADC while initializing the second tap of the DFE and holding the first tap of the DFE at a constant value.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: February 28, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Raghu Ganesan, Saravanakkumar Radhakrishnan, Gaurav Aggarwal, Rallabandi V Lakshmi Annapurna
  • Receiver circuit with interference detection
    Patent number: 11469785
    Abstract: A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC, and includes a notch filter. The interference detection path is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter. The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter to attenuate the interference signal.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: October 11, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Raghu Ganesan, Gaurav Aggarwal, Rahul Koppisetti, Rallabandi V Lakshmi Annapurna, Saravanakkumar Radhakrishnan, Kalpesh Laxmanbhai Rajai
  • Low power methods for signal processing blocks in ethernet PHY
    Patent number: 11316707
    Abstract: A method includes receiving an input signal at a filter, where the filter includes a plurality of filter taps, and where each of a first filter tap and a second filter tap has a weighting coefficient. The method also includes shutting down the first filter tap based on the weighting coefficient of the first filter tap being below a threshold and the weighting coefficient of the second filter tap being below the threshold, where the second filter tap is next to the first filter tap.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: April 26, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kalpesh Laxmanbhai Rajai, Saravanakkumar Radhakrishnan, Gaurav Aggarwal, Raghu Ganesan, Rallabandi V Lakshmi Annapurna
  • CLOCK RECOVERY AND CABLE DIAGNOSTICS FOR ETHERNET PHY
    Publication number: 20220052714
    Abstract: A receiver circuit includes an analog-to-digital converter (ADC), a decision feedback equalizer (DFE), a slicer, and a timing error detector (TED). The DFE is coupled to the ADC, and includes a first tap and a second tap. The slicer is coupled to the DFE. The TED is coupled to the slicer. The TED is configured to initialize timing of a sampling clock provided to the ADC while initializing the second tap of the DFE and holding the first tap of the DFE at a constant value.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 17, 2022
    Inventors: Raghu GANESAN, Saravanakkumar RADHAKRISHNAN, Gaurav AGGARWAL, Rallabandi V Lakshmi ANNAPURNA
  • LOW POWER METHODS FOR SIGNAL PROCESSING BLOCKS IN ETHERNET PHY
    Publication number: 20210288826
    Abstract: A method includes receiving an input signal at a filter, where the filter includes a plurality of filter taps, and where each of a first filter tap and a second filter tap has a weighting coefficient. The method also includes shutting down the first filter tap based on the weighting coefficient of the first filter tap being below a threshold and the weighting coefficient of the second filter tap being below the threshold, where the second filter tap is next to the first filter tap.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 16, 2021
    Inventors: Kalpesh Laxmanbhai RAJAI, Saravanakkumar RADHAKRISHNAN, Gaurav AGGARWAL, Raghu GANESAN, Rallabandi V. Lakshmi ANNAPURNA
  • RECEIVER CIRCUIT WITH INTERFERENCE DETECTION
    Publication number: 20210288684
    Abstract: A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC, and includes a notch filter. The interference detection path is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter. The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter to attenuate the interference signal.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 16, 2021
    Inventors: Raghu GANESAN, Gaurav AGGARWAL, Rahul KOPPISETTI, Rallabandi V Lakshmi ANNAPURNA, Saravanakkumar RADHAKRISHNAN, Kalpesh Laxmanbhai RAJAI