Abstract: An improved redundant computing apparatus includes a chassis assembly configured to (i) mount to a standard electronic equipment rack and (ii) consume substantially 1U of space in a particular direction (e.g., vertical height) within the standard electronic equipment rack. The chassis assembly includes a housing and a midplane disposed within the housing. The apparatus further includes a set of power supply/blower assemblies configured to connect to the midplane of the chassis assembly through a front of the housing in a field replaceable manner, and a set of computing devices configured to connect to the midplane of the chassis assembly through a back of the housing in a field replaceable manner. By way of example, the set of computing devices is adapted to move data into and out of a set of disk drives on behalf of a set of external host computers.

Abstract: Disclosed are ways of providing a highly flexible high availability storage system. Disk drive carriers for insertion into enclosures in a storage system include several disk drives. The enclosures accept carriers that include drives of different sizes, and drives compatible with different storage technologies, for instance Fibre Channel, SATA, or SAS. Drives oriented in their carriers in a manner that allows them to be connected to a common medium via identical flex circuits that are configured based on the orientation of the drives. Redundant controllers include redundant serial buses for transferring management information to the carriers. The carriers include a controller for monitoring the multiple serial buses and producing storage technology specific management commands for the disk drives.

Abstract: Disclosed are ways of providing a highly flexible high availability storage system. Disk drive carriers for insertion into enclosures in a storage system include several disk drives. The enclosures accept carriers that include drives of different sizes, and drives compatible with different storage technologies, for instance Fibre Channel, SATA, or SAS. Drives oriented in their carriers in a manner that allows them to be connected to a common medium via identical flex circuits that are configured based on the orientation of the drives. Redundant controllers include redundant serial buses for transferring management information to the carriers. The carriers include a controller for monitoring the multiple serial buses and producing storage technology specific management commands for the disk drives.

Abstract: Described is a storage system comprising a communication bus, a disk drive, a control board having a processing unit connected to the communication bus, and an adapter board in electrical communication with the disk drive. The adapter board has a controller connected to the communication bus. The controller receives instructions over the communication bus from the processing unit and communicates with the disk drive in response to the instructions. Optionally, the storage system has a midplane having a first connector connected to an electrical connector of the control board and a second connector connected to an electrical connector of the adapter board. Attached to opposite sides of the midplane, the first and second connectors are aligned with and electrically connected to each other through the midplane. An electrical signal transmitted between the control board and the adapter board passes directly through the midplane through the first and second midplane connectors.

Abstract: A computer system for managing a computer network comprises a rack cabinet having a cabinet interior. A plurality of infrastructure connector assemblies are fixedly mounted on the rack cabinet in 1-U boundaries, each infrastructure connector assembly including a signal snap interface connector and a power snap interface connector. A plurality of compute elements are adapted to be slidably disposed within the cabinet interior of the rack cabinet in a stacked relationship, each compute element including at least one infrastructure connector assembly which releasably snap-interconnects with an associated infrastructure connector assembly mounted on the rack cabinet. A distributed power bay is disposed within the rack cabinet and provides central power for the computer system. A rack manager is disposed within the rack cabinet and includes the central video and I/O devices for the computer system.

Abstract: An expandable memory system and a method for operating a memory system having a variable number of memory banks are described. The memory system can utilize a variable number of separately replaceable memory banks which can be implemented with memory element, such as dynamic random access memory chips, which are of differing speeds and or sizes. The memory system implements an interleaving of memory addresses among the memory banks as a function of the number of banks actually present so that successive memory accesses are not unnecessarily delayed by the recovery times of the memory elements. The memory system includes a programmable address decoder having a writable memory which provides bank address signals. Each of the banks includes a respective delay line for providing an output signal a respective presettable time after address signals are received by that bank for signalling to the host that data is ready to be transferred.

Abstract: A technique for generating gated clock signals for use in enabling various operating gating units in a data processing system in which an internal reference clock signal is used to generate both processor clock signals and the gated clock signals such that the latter signals are substantially synchronous with the processor clock signals. D-flip-flop circuitry together with a delay unit having an adjustable time delay are used to generate a gated clock signal. The overall time delay, from the time of which the circuitry is enabled until the gated clock signal is produced, is appropriately set by selecting the required time delay so that the overall time delay is essentially the same as the time delay required to generate the processor clock signals. Accordingly, the edges of the gated clock signals can be made to coincide with the edges of the processor clock signals.

Abstract: A method for performing address and data transfers among a plurality of different units of a data processing system having a system bus which includes an address bus and a data bus. The system uses arbitration phase, address transfer phase, and data transfer phase operations which require the use of unique handshake signals at each phase so as to permit address and data transfers to occur on a suitable priority basis with respect to different ones of such units in a pipelined manner using non-multiplexed, asynchronous operations.