Patents by Inventor Ralph C. Koester
Ralph C. Koester has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8055809Abstract: A system and associated method for distributing signals with efficiency over a microprocessor. A performance monitoring unit (PMU) sends configuration signals to a unit to monitor an event occurring on the unit. The unit is attached to a configuration bus and an event bus that are daisy-chained from PMU to other units in the microprocessor. The configuration bus transmits configuration signals from the PMU to the unit to set the unit to report the event. The unit sends event signals to the PMU through the event bus. The unit is configured upon receiving configuration signals comprising a base address of a bus ramp of the unit. A number of units and a number of events for monitoring is flexibly selected by adjusting a length of bit fields within configuration signals.Type: GrantFiled: December 24, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Matthias Fertig, Tilman Gloekler, Ralph C. Koester, Alexander Erik Mericas, Thomas Pflueger, Daniel Becker
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Patent number: 8024168Abstract: A method of generating debug data in a simulation environment includes generating a listing of one or more signals that relate to a failure signal; monitoring simulation data of the one or more signals for transitions between a defined state and an undefined state; and generating a waveform of data based on the transitions between the defined state and the undefined state.Type: GrantFiled: June 13, 2008Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Srinivas Venkata Naga Polisetty, Tilman Gloekler, Claudia Wolkober, Ralph C Koester
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Patent number: 7895426Abstract: A secure Power-on Reset (POR) engine is provided, inside a processor chip, which guarantees a secure initialization of the chip to enable secure code execution. External access to chip resources is limited to a very few targeted settings that do not compromise the chip security. The POR engine comprises a small state machine that runs through a predefined sequence coded in persistent memory contained in the processor chip. The state machine initializes the chip and allows external access from an external processor to only some scan chains of the processor chip in order to configure interfaces, and the like, without compromising the chip security. The state machine also manages the encryption keys that are used to verify that the code, fetched by the processor to complete the initialization in software, is not modified by a third party.Type: GrantFiled: August 24, 2007Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Ingemar Holm, Ralph C. Koester, Cedric Lichtenau, Thomas Pflueger, Mack W. Riley
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Publication number: 20100161867Abstract: A system and associated method for distributing signals with efficiency over a microprocessor. A performance monitoring unit (PMU) sends configuration signals to a unit to monitor an event occurring on the unit. The unit is attached to a configuration bus and an event bus that are daisy-chained from PMU to other units in the microprocessor. The configuration bus transmits configuration signals from the PMU to the unit to set the unit to report the event. The unit sends event signals to the PMU through the event bus. The unit is configured upon receiving configuration signals comprising a base address of a bus ramp of the unit. A number of units and a number of events for monitoring is flexibly selected by adjusting a length of bit fields within configuration signals.Type: ApplicationFiled: December 24, 2008Publication date: June 24, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthias Fertig, Tilman Gloekler, Ralph C. Koester, Alexander Erik Mericas, Thomas Pflueger
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Patent number: 7711875Abstract: A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.Type: GrantFiled: January 14, 2008Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventors: Tilman Gloekler, Ingemar Holm, Ralph C. Koester, Mack W. Riley
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Publication number: 20090313000Abstract: A method of generating debug data in a simulation environment includes generating a listing of one or more signals that relate to a failure signal; monitoring simulation data of the one or more signals for transitions between a defined state and an undefined state; and generating a waveform of data based on the transitions between the defined state and the undefined state.Type: ApplicationFiled: June 13, 2008Publication date: December 17, 2009Inventors: Srinivas Venkata Naga Polisetty, Tilman Gloekler, Claudia Wolkober, Ralph C. Koester
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Publication number: 20090222251Abstract: A design structure for a integrated circuit interfacing system may be embodied in a machine readable medium for designing, manufacturing or testing a integrated circuit. In one embodiment, the design structure specifies an integrated circuit that includes multiple interfaces. The design structure may specify that each of the interfaces couples to a respective set of registers or storage elements on the integrated circuit. The design structure may also specify a bridge circuit on the integrated circuit that switchably couples the two interfaces together such that one interface may communicate with the registers that associate with that interface as well as the registers that associate with the other interface.Type: ApplicationFiled: December 31, 2008Publication date: September 3, 2009Applicant: International Business Machines CorporationInventors: Tilman Gloekler, Ingemar Holm, Ralph C. Koester, Mack Wayne Riley, Shoji Sawamura, Iwao Takiguchi
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Publication number: 20090055637Abstract: A secure Power-on Reset (POR) engine is provided, inside a processor chip, which guarantees a secure initialization of the chip to enable secure code execution. External access to chip resources is limited to a very few targeted settings that do not compromise the chip security. The POR engine comprises a small state machine that runs through a predefined sequence coded in persistent memory contained in the processor chip. The state machine initializes the chip and allows external access from an external processor to only some scan chains of the processor chip in order to configure interfaces, and the like, without compromising the chip security. The state machine also manages the encryption keys that are used to verify that the code, fetched by the processor to complete the initialization in software, is not modified by a third party.Type: ApplicationFiled: August 24, 2007Publication date: February 26, 2009Inventors: Ingemar Holm, Ralph C. Koester, Cedric Lichtenau, Thomas Pflueger, Mack W. Riley
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Patent number: 7496692Abstract: Verifying configuration data for configuring a microprocessor or system-on-a-chip (SoC) is provided. During initialization, configuration data is shifted into the microprocessor or SoC through a configuration input. The configuration data is shifted to all of the on-chip processor units to provide initial settings for configuration latches in the design. While the configuration data is being shifted to the on-chip processor units, a copy of the configuration data is also stored in a local storage of a test control unit. A private interface is provided between the test control unit and the processor units. Via the private interface, a processor unit receives the current configuration data for the processor units. The current configuration data is compared against the original configuration data stored in the test control unit to verify the current configuration of the processor units.Type: GrantFiled: October 18, 2005Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventors: Ingemar Holm, Ralph C. Koester, John S. Liberty, Mack W. Riley
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Patent number: 7430624Abstract: A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.Type: GrantFiled: October 4, 2005Date of Patent: September 30, 2008Assignee: International Business Machines CorporationInventors: Tilman Gloekler, Ingemar Holm, Ralph C. Koester, Mack W. Riley
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Publication number: 20080147901Abstract: In one embodiment, the disclosed methodology and apparatus involves an integrated circuit that includes multiple interfaces. Each of the interfaces couples to a respective set of registers or storage elements on the integrated circuit. A bridge circuit on the integrated circuit switchably couples the two interfaces together such that one interface may communicate with the registers that associate with that interface as well as the registers that associate with the other interface.Type: ApplicationFiled: October 31, 2006Publication date: June 19, 2008Applicant: IBM CorporationInventors: Tilman Gloekler, Ingemar Holm, Ralph C. Koester, Mack Wayne Riley, Shoji Sawamura, Iwao Takiguchi
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Publication number: 20080133800Abstract: A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.Type: ApplicationFiled: January 14, 2008Publication date: June 5, 2008Inventors: Tilman Gloekler, Ingemar Holm, Ralph C. Koester, Mack W. Riley