Patents by Inventor Ralph Christopher Nieri
Ralph Christopher Nieri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9559644Abstract: Circuitry includes a floating-body main field-effect transistor (FET) device, a body-contacted cascode FET device, and biasing circuitry coupled to the floating-body main FET device and the body-contacted cascode FET device. The floating-body main FET device includes a gate contact, a drain contact, and a source contact. The body-contacted cascode FET device includes a gate contact, a drain contact coupled to a supply voltage, and a source contact coupled to the drain contact of the floating-body main FET device and to a body region of the body-contacted cascode FET device. The biasing circuitry is coupled to the gate contact of the floating-body main FET device and the gate contact of the body-contacted cascode FET device and configured to provide biasing signals to the floating-body main FET device and the body-contacted cascode FET device such that a majority of the supply voltage is provided across the body-contacted cascode FET device.Type: GrantFiled: November 3, 2015Date of Patent: January 31, 2017Assignee: Qorvo US, Inc.Inventors: George Maxim, Dirk Robert Walter Leipold, Baker Scott, Ralph Christopher Nieri
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Publication number: 20160126906Abstract: Circuitry includes a floating-body main field-effect transistor (FET) device, a body-contacted cascode FET device, and biasing circuitry coupled to the floating-body main FET device and the body-contacted cascode FET device. The floating-body main FET device includes a gate contact, a drain contact, and a source contact. The body-contacted cascode FET device includes a gate contact, a drain contact coupled to a supply voltage, and a source contact coupled to the drain contact of the floating-body main FET device and to a body region of the body-contacted cascode FET device. The biasing circuitry is coupled to the gate contact of the floating-body main FET device and the gate contact of the body-contacted cascode FET device and configured to provide biasing signals to the floating-body main FET device and the body-contacted cascode FET device such that a majority of the supply voltage is provided across the body-contacted cascode FET device.Type: ApplicationFiled: November 3, 2015Publication date: May 5, 2016Inventors: George Maxim, Dirk Robert Walter Leipold, Baker Scott, Ralph Christopher Nieri
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Patent number: 9244478Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.Type: GrantFiled: August 8, 2014Date of Patent: January 26, 2016Assignee: RF Micro Devices, Inc.Inventors: Nathaniel Peachey, Ralph Christopher Nieri
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Publication number: 20140347121Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.Type: ApplicationFiled: August 8, 2014Publication date: November 27, 2014Inventors: Nathaniel Peachey, Ralph Christopher Nieri
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Patent number: 8829981Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.Type: GrantFiled: May 8, 2013Date of Patent: September 9, 2014Assignee: RF Micro Devices, Inc.Inventors: Nathaniel Peachey, Ralph Christopher Nieri
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Publication number: 20140091858Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.Type: ApplicationFiled: May 8, 2013Publication date: April 3, 2014Applicant: RF Micro Devices, Inc.Inventors: Nathaniel Peachey, Ralph Christopher Nieri
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Patent number: 6838951Abstract: The present invention provides circuitry for maintaining the desired phase noise across the tuning range of a frequency synthesizer by compensating the voltage controlled oscillator (VCO) bias current according to various tuning parameters available within the frequency synthesizer, thereby reducing overall current drain and inductor quality factor requirements. In general, the present invention includes a VCO bias circuit capable of controlling the VCO bias current in response to a control signal provided by additional circuitry based on the operating frequency of the frequency synthesizer. Further, the VCO bias current changes in response to changing the operating frequency of the frequency synthesizer.Type: GrantFiled: June 3, 2003Date of Patent: January 4, 2005Assignee: RF Micro Devices, Inc.Inventors: Ralph Christopher Nieri, Scott Robert Humphreys, Tracy Hall
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Patent number: 6710664Abstract: The present invention provides an efficient coarse tuning process for fractional-N synthesizers. In general, a divided reference signal and a divided controllable oscillator (CO) signal from the phase lock loop (PLL) of a synthesizer are each further divided by a common factor M to provide an average reference signal and an average CO signal, respectively. Averaging the divided CO signal reduces jitter caused by fractional-N division of the CO signal. The frequencies of the average CO signal and the average reference signal are compared and the result is used to select an appropriate tuning curve for operating the CO.Type: GrantFiled: April 22, 2002Date of Patent: March 23, 2004Assignee: RF Micro Devices, Inc.Inventors: Scott Robert Humphreys, Ralph Christopher Nieri
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Publication number: 20030197564Abstract: The present invention provides an efficient coarse tuning process for fractional-N synthesizers. In general, a divided reference signal and a divided controllable oscillator (CO) signal from the phase lock loop (PLL) of a synthesizer are each further divided by a common factor M to provide an average reference signal and an average CO signal, respectively. Averaging the divided CO signal reduces jitter caused by fractional-N division of the CO signal. The frequencies of the average CO signal and the average reference signal are compared and the result is used to select an appropriate tuning curve for operating the CO.Type: ApplicationFiled: April 22, 2002Publication date: October 23, 2003Inventors: Scott Robert Humphreys, Ralph Christopher Nieri