Abstract: An apparatus for performing stuck fault testings within an integrated circuit is disclosed. A delay chain structure includes a first select register, a second select register, a decoder and a chain of multiplexors. With a set of select signals, the first select register generates a set of true encoded select signals, and the second select register generates a set of complement encoded select signals. Coupled to the first and second select registers, the decoder decodes the set of true encoded select signals and the set of complement encoded signals for controlling the chain of multiplexors. Each multiplexor within the chain of multiplexors is connected to one of the outputs of the decoder. The chain of multiplexors generates a single output value based on the set of select signals.

Abstract: A highly flexible system for performing a bitwrite operation on each bit of a Field Programmable Memory Array, while maintaining low-level routing requirements. The system consists of a bitwrite control subarray which is equal in width to the number of memory cells per word of a Field Programmable Memory Array and equal in height to 2N where N is the number chosen decode variations. Each cell of a Field Programmable Memory Array is associated via a bitwrite line with one cell of the bitwrite control subarray so that each cell can be independently controlled. The bitwrite control subarray can be programmed via a data bus prior to functional operation of the Field Programmable Memory Array, or while functional operation in the array continues.