Abstract: A wireless communications system and channel-switching method are disclosed herein. A source device and multiple sink devices independently maintain respective counters which track data packet errors. Each device independently switches channels only after its counter reaches a channel-switching threshold. The new channel switched-to is either determined by an indexed ordering of the available channels or by reference to a global clock maintained by each of the devices. Accordingly, all devices quickly arrive at a common channel. The system switches channels only when necessary and resolves quickly to a mutually acceptable channel. Therefore, unnecessary channel switching is minimized and data throughput is optimized.

Abstract: A wireless communications system and channel-switching method are disclosed herein. A source device and multiple sink devices independently maintain respective counters which track data packet errors. Each device independently switches channels only after its counter reaches a channel-switching threshold. The new channel switched-to is either determined by an indexed ordering of the available channels or by reference to a global clock maintained by each of the devices. Accordingly, all devices quickly arrive at a common channel. The system switches channels only when necessary and resolves quickly to a mutually acceptable channel. Therefore, unnecessary channel switching is minimized and data throughput is optimized.

Abstract: An improved receiver architecture and method for a wireless transceiver (e.g. for a headphone) is provided whereby the receiver, advantageously, enables the use of only one synthesizer circuit for both the RF-to-IF and IF-to-base band conversion processes which, in turn, provides for lower power consumption. The receiver includes an injection locked local receiver oscillator (Rx LO) which is used for the first mixing stage (i.e. the RF-to-IF conversion). The Rx LO 105 is thereby able to use a high-level harmonic of a relatively low reference frequency signal produced by that synthesizer (e.g. a fractional-N phase locked loop circuit (PLL)). The receiver further includes a tunable Q-enhanced IF filter 110 and complex sub-sampling and mixing down-conversion circuitry for the second conversion stage (i.e. IF-to-baseband conversion). The sampling frequency used for the second conversion stage is a harmonic of the reference frequency derived from the synthesizer (PLL).

Abstract: The invention relates to the field of electronics and more particularly to the tuning and injection locking of voltage controlled oscillators (VCOs). An improved injection locking circuit is provided which allows the VCO to injection lock with a smaller reference signal and therefore a smaller locking bandwidth (LBW). In order to allow the VCO to injection lock with a lower power reference signal, this invention includes a pre-tuning algorithm to place the VCO frequency such that the desired frequency is in the LBW. Tuning of the VCO is achieved using direct digital tuning that does not require an input reference. Injection locking is performed using a low frequency clock harmonic as the reference signal. More specifically, tuning is accomplished by sub-sampling and digitizing the output signal of the VCO, determining the center frequency, and adjusting the VCO control voltage.

Abstract: A power down system and method for an integrated circuit that enables a power down mode to be maintained for a predetermined time is described herein. The power down system comprises an oscillator, a low power oscillator and an oscillator control circuit controlling both the oscillator and the low power oscillator. The oscillator control circuit including at least one real time counter. The oscillator control circuit being so configured that the oscillator is energized when said oscillator control circuit is in a normal mode and that, when a power down signal is received: a) the oscillator control circuit measures an oscillation frequency of the low power oscillator, b) the oscillator control circuit uses the measured oscillation frequency of the low power oscillator to set the real time counter so as to maintain the power down mode for the predetermined time, c) the oscillator control circuit turns off the oscillator and uses the low power oscillator for the duration of the power down.

Abstract: The invention relates to electronic “sample and hold” circuits and, in particular, to such circuits which may implemented in integrated form. A method and circuit are provided for improving isolation during the hold mode of operation of a sampling circuit. An input differential signal is provided to parallel circuit paths (viz. a primary sampling path and an isolation path) which are identical (electronically equivalent) and, therefore, provide the same impedance leading to hold capacitor(s). The circuit paths are configured, relative to the differential inputs, so that any feed through (leakage) of the differential input signal is subtracted (cancelled) during the hold mode.

Abstract: A power down system and method for an integrated circuit that enables a power down mode to be maintained for a predetermined time is described herein. The power down system comprises an oscillator, a low power oscillator and an oscillator control circuit controlling both the oscillator and the low power oscillator. The oscillator control circuit including at least one real time counter. The oscillator control circuit being so configured that the oscillator is energized when said oscillator control circuit is in a normal mode and that, when a power down signal is received: a) the oscillator control circuit measures an oscillation frequency of the low power oscillator, b) the oscillator control circuit uses the measured oscillation frequency of the low power oscillator to set the real time counter so as to maintain the power down mode for the predetermined time, c) the oscillator control circuit turns off the oscillator and uses the low power oscillator for the duration of the power down.

Abstract: The invention relates to the field of electronics and more particularly to the tuning and injection locking of voltage controlled oscillators (VCOs). An improved injection locking circuit is provided which allows the VCO to injection lock with a smaller reference signal and therefore a smaller locking bandwidth (LBW). In order to allow the VCO to injection lock with a lower power reference signal, this invention includes a pre-tuning algorithm to place the VCO frequency such that the desired frequency is in the LBW. Tuning of the VCO is achieved using direct digital tuning that does not require an input reference. Injection locking is performed using a low frequency clock harmonic as the reference signal. More specifically, tuning is accomplished by sub-sampling and digitizing the output signal of the VCO, determining the center frequency, and adjusting the VCO control voltage.

Abstract: The invention relates to electronic “sample and hold” circuits and, in particular, to such circuits which may implemented in integrated form. A method and circuit are provided for improving isolation during the hold mode of operation of a sampling circuit. An input differential signal is provided to parallel circuit paths (viz. a primary sampling path and an isolation path) which are identical (electronically equivalent) and, therefore, provide the same impedance leading to hold capacitor(s). The circuit paths are configured, relative to the differential inputs, so that any feed through (leakage) of the differential input signal is subtracted (cancelled) during the hold mode.

Abstract: The invention relates to the field of microelectronics, more particularly to the structure and layout of integrated circuit capacitors. An integrated circuit capacitor is provided comprising: a first conductive component comprising a plurality of digital sub-components; and a second conductive component comprising a plurality of digital sub-components; wherein the digital sub-components of the first and second conductive components are interleaved and parallel, with a narrow uniform distance therebetween; and wherein the orientation of the interleaved digital sub-components is symmetrical about the center of the integrated circuit capacitor. This symmetrical orientation aids in the creation of a capacitor with well-matched top and bottom plates and capacitor pairs that have well-defined ratios. The arrangement serves to minimize the photolithographic variations by averaging the offsets caused by the different lithographic traces.