Abstract: Display integration schemes are described for passivating LEDs and providing conductive terminal connections. In accordance with embodiments, a sidewall passivation layer is formed around the LEDs. The sidewall passivation layer may or may not be contained within a well structure. A top electrode layer is formed to electrically connect the LEDs to conductive terminal routing.

Abstract: Display integration schemes are described for passivating LEDs and providing conductive terminal connections. In accordance with embodiments, a sidewall passivation layer is formed around the LEDs. The sidewall passivation layer may or may not be contained within a well structure. A top electrode layer is formed to electrically connect the LEDs to conductive terminal routing.

Abstract: A sensor array package can include a sensor disposed on a first side of a substrate. Signal trenches can be formed along the edges of the substrate and a conductive layer can be deposited in the signal trench and can couple to sensor signal pads. Bond wires can be attached to the conductive layers and can be arranged to be below a surface plane of the sensor. The sensor array package can be embedded in a printed circuit board enabling the bond wires to terminate at other conductors within the printed circuit board.

Abstract: A sensor array package can include a sensor disposed on a first side of a substrate. Signal trenches can be formed along the edges of the substrate and a conductive layer can be deposited in the signal trench and can couple to sensor signal pads. Bond wires can be attached to the conductive layers and can be arranged to be below a surface plane of the sensor. The sensor array package can be embedded in a printed circuit board enabling the bond wires to terminate at other conductors within the printed circuit board.

Abstract: A method of chemical vapor depositing a titanium nitride layer on a semiconductor wafer within a chemical vapor deposition reactor includes: a) positioning a wafer within a chemical vapor deposition reactor; b) injecting gaseous TiCl.sub.4, NH.sub.3 and N.sub.2 to within the reactor; and c) maintaining the reactor at a selected pressure and a selected temperature which are effective for reacting the TiCl.sub.4 and NH.sub.3 to deposit a uniform film comprising titanium nitride on the wafer, the selected temperature being less than or equal to about 500.degree. C. With a TiN film outwardly exposed, a wafer is annealed by the sequential steps of, a) rapid thermal processing the wafer having the outwardly exposed TiN film to a temperature from about 580.degree. C. to about 700.degree. C.; b) exposing the wafer to NH.sub.3 gas at a temperature from about 580.degree. C. to about 700.degree. C.

Abstract: A method and system for fabricating semiconductor wafers is disclosed wherein an atomically clean, semiconductor substrate having a surface is provided in a rapid thermal processing chamber. One embodiment involves cleaning the substrate by exposing it to a first gas at a temperature substantially within the range of 850.degree. C. to 1250.degree. C. for approximately 10 to 60 seconds. Subsequently, a coating having a first thickness is formed superjacent the substrate surface by introducing a second gas at a temperature substantially within the range of 850.degree. C. to 1250.degree. C. for approximately 5 to 30 seconds in the chamber. The resultant coating, depending on the gas selected, comprises either SiO.sub.2 or Si-F.Subsequently, the substrate having the coating is exposed to a third gas at a temperature substantially within the range of 900.degree. C. to 1050.degree. C. for approximately 30 minutes to one hour, thereby forming a silicon dioxide layer.