Abstract: The present invention provides an FFT/IFFT processor for use with N data values. In one embodiment, the FFT/IFFT processor includes an even-odd data mapper configured to provide a mapping of the N data values into N/2 mapped complex data values if the N data values are real. Additionally, the FFT/IFFT processor also includes a separator-combiner, coupled to the even-odd data mapper, configured to compute either an FFT based on the mapping or an IFFT based on the N data values if the N data values are complex.

Abstract: A method of performing a pattern fill operation of a pattern into a clipping region divides dividing the pattern into a plurality of bands. For each band the method renders the band as a bit map into a band cache. For each tiling of the pattern into the clipping region the method clips the bit map of a current band to the clipping region and copies the clipped bit map into a corresponding location of a page bit map. The plurality of bands of the pattern are preferable aligned with scan lines of the printed page. The bands may correspond to individual scan lines. The method select the number of bands so that each band may be stored within a predetermined amount of band cache memory.

Abstract: A method of performing a pattern fill operation of a pattern into a clipping region resolves the pattern into an intermediate format between a page description language and a page bit map. This intermediate format is cached. For each tiling of the pattern into the clipping region the pattern is clipped to the clipping region and rendered from the clipped intermediate format pattern into a corresponding location of a page bit map. The intermediate format of the pattern may be scan line runs and trapezoid fills. The intermediate format of the pattern may be paths and curves. The clipping of the pattern to the clipping region performs scan line conversion with polygon to polygon clipping or trapezoid/run array to trapezoid/run array clipping.

Abstract: A data processing system comprises an input controller and an execution unit operating in a pipelined mode, where the execution unit converts the input from a page description language representation to a display list representation. The display list is further processed by a font cache server, a display list server and a source list server. The output from these servers is coupled to multiple rendering engines, which operate in parallel to generate a bitmap representation of the input data.

Abstract: A system for data communication is disclosed that comprises a hybrid circuit (220) that receives a signal. A switched gain circuit (204) coupled to the hybrid circuit (220) receives the signal from the hybrid circuit (220). A receiver circuit (206) coupled to the switched gain circuit (204) receives the signal from the switched gain circuit (204). The switched gain circuit (204) adjusts the power of the signal transmitted to the receiver circuit (206). More specifically, the switched gain circuit (204) detects the power of the signal received from the hybrid circuit (220), and adjusts the power of the signal transmitted to the receiver circuit (206) based upon the power of the signal received from the hybrid circuit (220). A method for data communication is disclosed. A signal is received using a hybrid circuit (220). The signal is transmitted to a switched gain circuit (204) coupled to the hybrid circuit (220). The power of the signal is adjusted using the switched gain circuit (204).

Abstract: A method of performing a pattern fill operation of a pattern into a clipping region resolves the pattern into an intermediate format between a page description language and a page bit map. This intermediate format is cached. For each tiling of the pattern into the clipping region the pattern is clipped to the clipping region and rendered from the clipped intermediate format pattern into a corresponding location of a page bit map. The intermediate format of the pattern may be scan line runs and trapezoid fills. The intermediate format of the pattern may be paths and curves. The clipping of the pattern to the clipping region performs scan line conversion with polygon to polygon clipping or trapezoid/run array to trapezoid/run array clipping.

Abstract: A method of performing a pattern fill operation of a pattern into a clipping region divides dividing the pattern into a plurality of bands. For each band the method renders the band as a bit map into a band cache. For each tiling of the pattern into the clipping region the method clips the bit map of a current band to the clipping region and copies the clipped bit map into a corresponding location of a page bit map. The plurality of bands of the pattern are preferable aligned with scan lines of the printed page. The bands may correspond to individual scan lines. The method select the number of bands so that each band may be stored within a predetermined amount of band cache memory.

Abstract: A printer forms an approximate of a Bezier curve as a sequence of line segments. Two parametric equations, X(t) and Y(t), are employed. Two methods can be used to evaluate the parametric equations. Both use fixed point integer arithmetic to directly calculate points along the curve which are the values of the X(t) and Y(t) equations. The first method sets the number of steps of the parametric variable are equal to an integral power of 2. This gives a predictable execution time and uses line segments to connect the points as a piecewise straight line approximation to the curve. The number of steps is set as the next higher power of 2 than an estimated length of the curve. The second method allows Y(t), the scan line variable, to change only in predetermined integer steps. The value of X(t) is evaluated for each t corresponding to the integer step in Y(t). This second method has a natural advantage, if a closed path is being decomposed as a run array rather than a collection of trapezoids.

Abstract: A digital subscriber line modem (30) capable of operating with multiple transmission line profiles depending on the current transmission line characteristics of a wire line pair (20) includes an interface (212, 292) to the wire line pair (20) and a signal converter (214, 290) with a terminal coupled to the interface. An on/off-hook detector(300) drives an impedance analyzer function (304) that is able to measure transmission line parameters based on the current line characteristics of the wire line pair (20). A control logic block (310) performs the actions required to adapt to a new line conditions of the wire line pair (20) and rapidly adapt to the new on/off hook condition.

Abstract: A method of processing print data allowing for rendering bands of print data in parallel. A main processor (52) of a single-chip multiprocessor converts an incoming page of print data into paths. The paths are then converted to primitives and the primitives are rasterized using parallel processor (60, 62, 64, 66). The parallel processors (60, 62, 64, 66) work in concert with the main processor (52) such that bands of the final print image are rendered into a frame buffer (58) in parallel, allowing for faster and more efficient processing of print data.

Abstract: A block based hybrid compression method where the input page is classified as SOLID, TEXT, SATURATED TEXT or IMAGE type, and the compression method most appropriate for each class is chosen on a block by block basis. Blocks classified as IMAGE may be compressed using Parallel Differential Pulse Code Modulation. This method allows the decompression algorithm to decode multiple pixels in parallel, thus making real time decompression significantly easier to implement. The methods shown will execute very efficiently on a Texas Instruments TMS302C82 multiprocessing Digital Signal Processor.

Abstract: A system for data communication is disclosed that comprises a hybrid circuit (220) that receives a signal. A switched gain circuit (204) coupled to the hybrid circuit (220) receives the signal from the hybrid circuit (220). A receiver circuit (206) coupled to the switched gain circuit (204) receives the signal from the switched gain circuit (204). The switched gain circuit (204) adjusts the power of the signal transmitted to the receiver circuit (206). More specifically, the switched gain circuit (204) detects the power of the signal received from the hybrid circuit (220), and adjusts the power of the signal transmitted to the receiver circuit (206) based upon the power of the signal received from the hybrid circuit (220). A method for data communication is disclosed. A signal is received using a hybrid circuit (220). The signal is transmitted to a switched gain circuit (204) coupled to the hybrid circuit (220). The power of the signal is adjusted using the switched gain circuit (204).

Abstract: A processing unit for a printer system. The processing unit is comprised of a master processor and multiple parallel processors. The master processor builds the display list from a page description program or from some other graphics programming. It partitions the display list into sublists and distributes the sublists to the parallel processors. The parallel processors interpret the sublists, thereby rendering the image as bitmapped data.

Abstract: A processing unit (11) for a printer system. The processing unit (11) is comprised of a master processor (21) and multiple parallel processors (22). The master processor (21) builds a display list and partitions it into sublists, which it distributes to the parallel processors (22). The parallel processors (22) interpret the sublists, thereby rendering the image as bitmapped data. Interpretation of a sublist is performed by reading its operation codes and calling rasterizing primitives represented by the operation codes. (FIG. 3). During execution of a rasterizing primitive, a parallel processor (22) determines whether the next operation code in the sublist will call the same primitive. If so, execution of the current primitive is repeated.