Abstract: An apparatus for handling data at two or more ports is described. In one embodiment, the apparatus comprises an apparatus for receiving data at multiple ports, each port having a buffer capable of holding B units of received data and being serviced by a processor resource. The apparatus has software causing the processor resource to have a polling session with each port and to read unread units of data from the buffer in each port during its polling session. It also has a counter for determining the number of units of data that have been read from the buffer and circuitry responsive to said counter to assert flow control from said port based on the number of units of data read.

Abstract: An improved Packet Assembler/Disassembler (PAD) optimizes the assembling of characters into packets for transmission over a packet network. The PAD is arranged to operably connect to and receive character asynchronous data from one or more terminal instruments operating in either a block transfer mode or an echoplexing mode. Characters received by the PAD from a terminal instrument operating in an echoplexing mode are forwarded with no PAD delay. Characters received by the PAD from a terminal instrument operating in a block transfer mode are similarly forwarded with no PAD delay and in full packets with the exception of the last few characters of each block of characters which only partially fill their respective packets. And these partially filled packets are quickly forwarded in a time period which just exceeds the period required for the reception of a single character at the rate of data reception from the terminal instrument.

Abstract: An asynchronous interface for coupling data between a terminal and a data module is provided. The asynchronous interface directly determines and matches to the rate of serial data being transmitted by the terminal and received by the data module with minimal involvement of a processor associated with the data module. The asynchronous interface determines the rate of the data being transmitted by configuring counting circuitry therein for measuring the period of the start bit in the first received character whenever the speed of data being transmitted by the terminal must be determined. The asynchronous interface then adjusts to the newly determined data rate and receives the remaining bits in the first character and subsequent characters at the new rate. The processor is involved only to request that the asynchronous interface determine the incoming data rate and match to it and, once the data rate has been determined and matched, to process the recovered characters and this new rate.

Abstract: A system for analyzing images represented by a serial stream of digital electrical signals corresponding to values of pixels in a matrix of points constituting an image. The system includes a pipeline of substantially identical neighborhood transformation stages. Each stage includes a processor portion for analyzing the pixel values and a memory portion communicating with the processor portion for sequentially providing a window of neighboring pixels to the processor for analysis. A central programmable controller communicates with the pipeline over a single communication link which provides both the pixel value data to the pipeline and transformation control instructions to the processor portions of each stage. The memory portion preferably includes a random access memory which serves as a line storage device which may be readily adjusted to accommodate different raster scan line lengths from various image sensors.

Abstract: A system for analyzing images represented by a plurality of raster scan lines of pixel values employs at least one neighborhood transformation stage. The stage includes a processor portion for analyzing windows of neighboring pixel values and providing a transformation output as a function of the pixel values contained in the window. A random access memory (RAM) repetitively stores a given plurality of successive pixel scan lines fed to the stage. Selected pixel values from the RAM are loaded into the processor portion so as to sequentially access the neighborhood windows for analysis. The RAM serves as a recirculating line storage device for accommodating different raster scan line lengths.

Abstract: An image analyzer system and a method of analyzing image information contained in serial scan lines of pixels in which some of the pixels have valid data values representing image information while other pixels have invalid data values not representing characteristics of the image to be analyzed. Off image detector circuitry is utilized to generate output signals to neighborhood transformation logic when one or more pixels in a neighborhood contain invalid values. Preferably, the off image detector means monitors the status of a control line which indicates whether valid or invalid pixels are being transferred over a bus to a stage of the image analyzer system. The detector circuitry operates to store the number of valid pixels in subsequent scan lines presented to the stage. This comparison is utilized to detect invalid pixel values which may be contained in each neighborhood.

Abstract: An image analyzer system employs one or more neighborhood transformation stages. The stage operates to access groups of neighboring pixels in an image matrix, analyzes them and generates a transformation output as a result of the analysis. The stage includes a logic circuit which is programmable from a central controller. In the preferred embodiment, each pixel in the neighborhood is analyzed by the logic circuit and temporarily stored until other pixels in the group have been analyzed. The combination of analyzed pixel values form the basis for generating the transformation output for the stage. Preferably, the logic circuit is designed to perform both two dimensional and three dimensional image analyses.