Abstract: A memory board can be assembled with one, two or more rows of memory chips to provide a corresponding number of different memory capacities for expanding the capacity of main memory which resides on a basic logic board containing the processing units and other units of a system. The memory board includes a programmable read only memory (PROM) circuit which receives as inputs from the basic logic board a predetermined address portion of each memory address together with memory refresh and timing signals. The PROM circuit is coded in a predetermined manner for generating at its output terminals row address select (RAS) pulse output signals to a row or block of memory chips designated by the predetermined address portion. The pulse widths of the output signals are established by the timing signal applied to an enabling terminal of the PROM.

Abstract: An adapter includes free running low power clock circuits connected to provide a time of day value accessible by a central processing unit which couples to the adapter through a controller subsystem. The adapter cicuits are constructed on a circuit board which is installed as part of the controller subsystem. The clock circuits are connected to one terminal of a battery power supply whose other terminal connects to an interface connector included within the adapter. Upon installing the adapter board in the subsystem, the battery power supply is connected to provide power for operating the clock circuits. When the adapter is removed from the subsystem, the battery power supply is disconnected, preventing it from discharging. The adapter includes an adapter connector for connecting the output terminal of the battery power supply to enable the battery to be charged or its power level monitored when the adapter circuit board is installed.

Abstract: Clock logic for generating multiple clock pulses during a single clock cycle. In response to a signal indicative of a clock cycle, effectively two clock pulses are produced in a relatively short period of time. Such logic, which includes a delay element, causes first a load pulse to be produced thereby enabling the loading of information into, for example, a register. Additionally, and within the same clock cycle as the load pulse and in response to the same signal, an increment pulse is produced to, for example, increment a counting function which may be included in such register.