Abstract: A method for representing a layout of an integrated circuit (IC) includes, in part, determining multiple regions of the IC layout based on one or more parameters, determining multiple areas associated with the multiple regions where each area has a characteristic of a region of the multiple regions, assigning a first set of values to locations of the IC layout outside the multiple areas, assigning a second set of values to locations of the IC layout within the multiple areas, and, in response to a determination that a location of the IC layout is in two or more overlapping areas of the multiple areas, determining a value to assign to the location in accordance with the values of the two or more overlapping areas. The method further includes generating data representative of the IC layout design in accordance with the first and second set of values, and the assigned value.

Abstract: Embodiments provide a method for representing a layout of an integrated circuit. In example embodiments, a method includes determining multiple regions of an integrated circuit (IC) layout design based on one or more parameters. In embodiments, at least one region of the multiple regions has a characteristic. The example method further includes determining multiple areas associated with the multiple regions. Each area of the multiple areas has a characteristic of a region of the multiple regions.

Abstract: A method and apparatus of a novel modeling scheme for performing optical lithography simulation for a multi-color layer fabrication process is described. The method interpolates for simulation use between test or experimental data or descriptions to more accurately apply color differentiated parameters to the model creation and lithography simulation.

Abstract: A method to evaluate a resistor structure is described. In one embodiment, the method includes receiving an input file specifying a resistor structure, modifying at least one aspect of the resistor structure, and polishing data representing the modified resistor structure. The method further comprises, in one embodiment, initializing at least one walk, and performing the walk, and providing an output about the resistor structure based on the performed at least one walk.

Abstract: A method to evaluate a resistor structure is described. In one embodiment, the method includes receiving an input file specifying a resistor structure, modifying at least one aspect of the resistor structure, and polishing data representing the modified resistor structure. The method further comprises, in one embodiment, initializing at least one walk, and performing the walk, and providing an output about the resistor structure based on the performed at least one walk.

Abstract: A method and apparatus of a novel modeling scheme for performing optical lithography simulation for a multi-color layer fabrication process is described. The method interpolates for simulation use between test or experimental data or descriptions to more accurately apply color differentiated parameters to the model creation and lithography simulation.

Abstract: The strain relief device is used in combination with a metal electronic cable-connector assembly for high temperature applications and high mechanical shock application. The strain relief shrouds and protects the weld or braze between the cable and connector and also extends over a length of the cable to brace it from bending stress ad strain. The strain relief is generally hollow and tubular, an expanded end thereof being slip fitted over and/or welded to or threaded into an end of the connector and caused to extend over the cable-connector weld or braze, with a narrow end of the strain relief forming a lip surrounding the cable distal of the weld or braze to brace it. Thus, the cable and described connector end fit into the central longitudinal passageway in the strain relief and are enclosed by it. The strain relief can be in a form such that its central portion extends through a bulkhead and can be locked thereto.