Patents by Inventor Ralph J. Jaccodine

Ralph J. Jaccodine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chemically enhanced thermal oxidation and nitridation of silicon and products thereof
    Patent number: 5043224
    Abstract: A process for enhanced thermal oxidation and nitridation of silicon by introduction of fluorine into the oxidation and nitridation ambients.
    Type: Grant
    Filed: April 5, 1990
    Date of Patent: August 27, 1991
    Assignee: Lehigh University
    Inventors: Ralph J. Jaccodine, Paul Schmidt, deceased, Eva Schmidt, executrix
  • Silicon integrated circuits
    Patent number: 4353086
    Abstract: A dynamic random access memory in which individual cells, including an access transistor and a storage capacitor, are formed in mesas formed on a silicon chip. The access transistor of the cell is formed on the top surface of the mesa and one plate of the storage capacitor of the cell is formed by the sidewall of the mesa and the other plate by doped polycrystalline silicon which fills the grooves surrounding the mesas isolated therefrom by a silicon dioxide layer. By this geometry, large storage surfaces, and so large capacitances, can be obtained for the capacitor without using surface area of the chip. In other embodiments, the mesas may include other forms of circuit elements.
    Type: Grant
    Filed: May 7, 1980
    Date of Patent: October 5, 1982
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Ralph J. Jaccodine, John A. Michejda
  • Insulation layer reflow
    Patent number: 4284659
    Abstract: This disclosure is directed to a method of forming an interlevel dielectric glass layer (16) on a semiconductor device, the layer having a plurality of feed-through apertures (17--17) therein. A CW laser beam (29) is continuously raster scanned over the surface of the glass layer (16) to reflow the layer to densify the material and form a smooth surface topography about the apertures (17--17).
    Type: Grant
    Filed: May 12, 1980
    Date of Patent: August 18, 1981
    Assignees: Bell Telephone Laboratories, Western Electric Co., Inc.
    Inventors: Ralph J. Jaccodine, Ami Kestenbaum
  • Silicon integrated circuits
    Patent number: RE32090
    Abstract: A dynamic random access memory in which individual cells, including an access transistor and a storage capacitor, are formed in mesas formed on a silicon chip. The access transistor of the cell is formed on the top surface of the mess and one plate of the storage capacitor of the cell is formed by the sidewall of the mesa and the other plate by doped polycrystalline silicon which fills the grooves surrounding the mesas isolated therefrom by a silicon dioxide layer. By this geometry, large storage surfaces, and so large capacitances, can be obtained for the capacitor without using surface area of the chip. In other embodiments, the mesas may include other forms of circuit elements.
    Type: Grant
    Filed: October 5, 1984
    Date of Patent: March 4, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: Ralph J. Jaccodine, John A. Michejda