Abstract: An integrated circuit system and program product for predicting yield of a VLSI design. An integrated circuit system is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.

Abstract: A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.

Abstract: An integrated circuit and program product for predicting yield of a VLSI design. An integrated circuit is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.

Abstract: A system, method and program product for predicting yield of a VLSI design. A method is provided including the steps of: identifying and grouping sub-circuits contained within an integrated circuit design by type; calculating critical area values for regions within the integrated circuit design; and applying different yield models to critical area values based on the types of the regions used to calculate the critical area values, wherein each yield model is dependent on a type.

Abstract: A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.

Abstract: A system and method for visualizing data. Data are provided either in the form of data values of a data array or in the form of a geometric representation. A data array may be, for example, a sparse matrix. A geometric representation, may be, for example, an integrated circuit layout coded in a geometric description language. Data provided in the form of data values are associated with geometric shapes placed on a grid. Information placed on the grid is then reported to a user. If data are provided in the form of a geometric representation, then data values are extracted from the geometric representation. A graphic representation is generated from the extracted data values. The graphic representation is exhibited to a user.

Abstract: Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.

Abstract: The present invention divides a large graphics file into smaller “frames” of graphics files. The division process is preferably load balanced amongst any number of processors. This allows many processors to be used in parallel to divide the large graphics file and to then process the smaller output frames. Additionally, the load balancing is performed in such a manner that only portions of the graphics file need be loaded by any one processor. This saves memory and computational requirements. Preferably, the graphics file is divided in a three-dimensional manner, such that any one processor will be assigned one three-dimensional block or volume of the graphics file. The three-dimensional partition of the graphics file will become one frame, and the one processor accesses the graphics file to copy its three-dimensional partition into the new output frame.

Abstract: A method is provided for designing an integrated circuit that includes receiving a graphical description of the integrated circuit, extracting shapes relating to a specific circuit function from the graphical description of the integrated circuit, and partitioning the extracted shapes into a plurality of segments. The method may form an electrical representation of the integrated circuit for each of the plurality of segments and solve a matrix equation (Gv=i) for each of the plurality of segments based on the electrical representation.

Abstract: A system and method for visualizing data. Data are provided either in the form of data values of a data array or in the form of a geometric representation. A data array may be, for example, a sparse matrix. A geometric representation, may be, for example, an integrated circuit layout coded in a geometric description language. Data provided in the form of data values are associated with geometric shapes placed on a grid. Information placed on the grid is then reported to a user. If data are provided in the form of a geometric representation, then data values are extracted from the geometric representation. A graphic representation is generated from the extracted data values. The graphic representation is exhibited to a user.

Abstract: A method for manufacturing an integrated circuit having improved defect-limited yield. Each conductor on the integrated circuit is represented as an electrical element of a network, having branch voltages and currents. The width of the conductor is advantageously selected to have the minimum width necessary to produce signal levels that have sufficient noise margins. An integrated circuit conductive grid is thus realized having a reduced cross sectional area along a portion of various conductor element lengths, to reduce the risk that particles produced during manufacturing will result in bridging of adjacent conductor elements.

Abstract: Disclosed is a system and method of providing performance analysis on integrated circuit devices and systems using an IEEE JTAG 1149.1 interface. An integrated circuit device is described that includes an execution control register for receiving a control code from an external device via the JTAG interface, a means for selecting and coupling to one or more specific logic circuits on the device, one or more counters for recording specific events occurring on the logic circuits, and a counter register for managing the counter data and outputting it via the JTAG interface.

Abstract: An armrest for a seat such as a stool having a post extending upwardly from an edge of the seat and supporting a substantially horizontal arm which is connected to the upper end of the post by a one-way clutch permitting pivotal movement of the arm in one direction around the axis of the post but preventing reverse pivotal movement of the arm and the mounting of the clutch on the post permitting limited vertical movement of the arm and clutch relative to the post to deactivate the clutch relative to the post to permit rotation of the arm relative to the post in the aforementioned reverse direction thereof.

Abstract: A safety air gap system for an exemplary high volume evacuator having a water-sealed pump to provide suction thereto and including a gray water discharge from the pump to a drain, the system including a closed housing adapted to be mounted at a higher level than the evacuator, a reservoir for fresh water in the housing terminating a predetermined distance below the top, a coaxial pair of inner and outer tubes extending upward from the bottom of the reservoir and terminating above the top of the reservoir, the lower end of the inner tube receiving municipal water for discharge at the top to the outer tube which discharges the water at the lower end to the reservoir as controlled by a float-operated valve between the upper ends of the tubes, the housing having in one sidewall an outlet port connectable to a drain at a level below the top of the reservoir to prevent accidental filling of the housing with water in the event of a malfunction of the system, and an air gap opening positioned in a sidewall of the hou

Abstract: An operatory chair, such as a dental chair, having an upper supporting member to which the seat and back unit of an operatory chair may be attached, particularly pertaining to the mechanism by which said supporting member for the seat and back is raised and lowered. The preferred construction comprises a pair of sets of pivotally connected links arranged in lazy tong manner, said links being operated by linkage mechanism actuated by a rotatable screw and follower in such manner that the movement of the supporting member for the seat and back is smooth and relatively slow, particularly at the commencement of elevating movement so as not to include sudden and rapid upward movement as is conventional with typical lazy tong structures used in jacks and the like.