Patents by Inventor Ralph Jan-Pin Lu
Ralph Jan-Pin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10770363Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate, the thermal control elements defining heater zones each of which is powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones. A power distribution circuit is mated to a baseplate of the substrate support, the power distribution circuit being connected to each power supply line and power return line of the heater array. A switching device is connected to the power distribution circuit to independently provide time-averaged power to each of the heater zones by time divisional multiplexing of a plurality of switches.Type: GrantFiled: August 7, 2018Date of Patent: September 8, 2020Assignee: Lam Research CorporationInventors: Keith William Gaff, Tom Anderson, Keith Comendant, Ralph Jan-Pin Lu, Paul Robertson, Eric A. Pape, Neil Benjamin
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Publication number: 20180374763Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate, the thermal control elements defining heater zones each of which is powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones. A power distribution circuit is mated to a baseplate of the substrate support, the power distribution circuit being connected to each power supply line and power return line of the heater array. A switching device is connected to the power distribution circuit to independently provide time-averaged power to each of the heater zones by time divisional multiplexing of a plurality of switches.Type: ApplicationFiled: August 7, 2018Publication date: December 27, 2018Inventors: Keith William Gaff, Tom Anderson, Keith Comendant, Ralph Jan-Pin Lu, Paul Robertson, Eric A. Pape, Neil Benjamin
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Patent number: 10049948Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate, the thermal control elements defining heater zones each of which is powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones. A power distribution circuit is mated to a baseplate of the substrate support, the power distribution circuit being connected to each power supply line and power return line of the heater array. A switching device is connected to the power distribution circuit to independently provide time-averaged power to each of the heater zones by time divisional multiplexing of a plurality of switches.Type: GrantFiled: November 30, 2012Date of Patent: August 14, 2018Assignee: LAM RESEARCH CORPORATIONInventors: Keith William Gaff, Tom Anderson, Keith Comendant, Ralph Jan-Pin Lu, Paul Robertson, Eric A. Pape, Neil Benjamin
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Publication number: 20140154819Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate, the thermal control elements defining heater zones each of which is powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones. A power distribution circuit is mated to a baseplate of the substrate support, the power distribution circuit being connected to each power supply line and power return line of the heater array. A switching device is connected to the power distribution circuit to independently provide time-averaged power to each of the heater zones by time divisional multiplexing of a plurality of switches.Type: ApplicationFiled: November 30, 2012Publication date: June 5, 2014Applicant: LAM RESEARCH CORPORATIONInventors: Keith William Gaff, Tom Anderson, Keith Comendant, Ralph Jan-Pin Lu, Paul Robertson, Eric A. Pape, Neil Benjamin
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Patent number: 8315029Abstract: A plasma processing system for processing a wafer is provided. The system includes an electrostatic chuck (ESC) positioned inside a plasma processing chamber and configured to support the wafer. The ESC includes a positive terminal for providing a first force to the wafer and a negative terminal for providing a second force to the wafer. The system also includes a first circuit arrangement configured to measure at least a first voltage for determining a value of a positive load current applied to the positive terminal. The system further includes a second circuit arrangement configured to measure at least a second voltage for determining a value of a negative load current applied to the negative terminal. The system yet also includes circuitry configured to adjust a bias voltage using the values of the positive load current and the negative load current for balancing the first force and the second force.Type: GrantFiled: July 18, 2011Date of Patent: November 20, 2012Assignee: Lam Research CorporationInventors: Seyed Jafar Jafarian-Tehrani, Ralph Jan-Pin Lu
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Publication number: 20120018095Abstract: A plasma processing system for processing a wafer is provided. The system includes an electrostatic chuck (ESC) positioned inside a plasma processing chamber and configured to support the wafer. The ESC includes a positive terminal for providing a first force to the wafer and a negative terminal for providing a second force to the wafer. The system also includes a first circuit arrangement configured to measure at least a first voltage for determining a value of a positive load current applied to the positive terminal. The system further includes a second circuit arrangement configured to measure at least a second voltage for determining a value of a negative load current applied to the negative terminal. The system yet also includes circuitry configured to adjust a bias voltage using the values of the positive load current and the negative load current for balancing the first force and the second force.Type: ApplicationFiled: July 18, 2011Publication date: January 26, 2012Inventors: Seyed Jafar Jafarian-Tehrani, Ralph Jan-Pin Lu
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Patent number: 7983018Abstract: An arrangement for securing a wafer during substrate processing is provided. The arrangement includes a power supply and an electrostatic chuck (ESC). The ESC supports the wafer and includes a positive and a negative terminal. A positive high voltage is provided to the positive terminal through an RF filter and a negative high voltage is provided to the negative terminal through the RF filter. The arrangement also includes a first and a second trans-impedance amplifiers (TIAs) that measure a first set of voltages for determining a value of a positive load current applied to the positive terminal and a third and fourth TIAs that measure a second set of voltages for determining a value of a negative load current applied to the negative terminal. The arrangement yet also includes a program to adjust a bias voltage using the values of the positive load current and the negative load current.Type: GrantFiled: August 2, 2010Date of Patent: July 19, 2011Assignee: Lam Research CorporationInventors: Seyed Jafar Jafarian-Tehrani, Ralph Jan-Pin Lu
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Publication number: 20110051307Abstract: An arrangement for securing a wafer during substrate processing is provided. The arrangement includes a power supply and an electrostatic chuck (ESC). The ESC supports the wafer and includes a positive and a negative terminal. A positive high voltage is provided to the positive terminal through an RF filter and a negative high voltage is provided to the negative terminal through the RF filter. The arrangement also includes a first and a second trans-impedance amplifiers (TIAs) that measure a first set of voltages for determining a value of a positive load current applied to the positive terminal and a third and fourth TIAs that measure a second set of voltages for determining a value of a negative load current applied to the negative terminal. The arrangement yet also includes a program to adjust a bias voltage using the values of the positive load current and the negative load current.Type: ApplicationFiled: August 2, 2010Publication date: March 3, 2011Inventors: Seyed Jafar Jafarian-Tehrani, Ralph Jan-Pin Lu
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Patent number: 7768766Abstract: A plasma processing system is disclosed. The plasma processing system may include an electrostatic chuck (ESC) positioned inside a plasma processing chamber and configured to support a wafer. The ESC may include a positive terminal (+ESC) for providing a first force to the wafer and a negative terminal (?ESC) for providing a second force to the wafer. The plasma processing system may also include a first trans-impedance amplifier (TIA) and a second TIA configured to measure a first set of voltages for calculating a value of a positive load current applied to the positive terminal. The plasma processing system may also include a third TIA and a fourth TIA configured to measure a second set of voltages for calculating a value of a negative load current applied to the negative terminal.Type: GrantFiled: June 28, 2007Date of Patent: August 3, 2010Assignee: Lam Research CorporationInventors: Seyed Jafar Jafarian-Tehrani, Ralph Jan-Pin Lu
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Publication number: 20080297971Abstract: A plasma processing system is disclosed. The plasma processing system may include an electrostatic chuck (ESC) positioned inside a plasma processing chamber and configured to support a wafer. The ESC may include a positive terminal (+ESC) for providing a first force to the wafer and a negative terminal (?ESC) for providing a second force to the wafer. The plasma processing system may also include a first trans-impedance amplifier (TIA) and a second TIA configured to measure a first set of voltages for calculating a value of a positive load current applied to the positive terminal. The plasma processing system may also include a third TIA and a fourth TIA configured to measure a second set of voltages for calculating a value of a negative load current applied to the negative terminal.Type: ApplicationFiled: June 28, 2007Publication date: December 4, 2008Inventors: Seyed Jafar Jafarian-Tehrani, Ralph Jan-Pin Lu