Abstract: An error detector provides an output pulse whenever an error is detected in the framing pattern of a digital transmission system. A sample timer provides a sample pulse at the beginning of each sample interval and a sample clock pulse during the sample pulse. The sample interval includes a plurality of frames and the sample pulse occurs intermediate of the framing pattern. A logic arrangement is responsive to the error output pulse, the sample clock pulse and the sample pulse for providing an alarm indication when the number of error pulses equals or exceeds a first predetermined number during a sample interval. Conversely, the logic arrangement eliminates the alarm indication if the number of errors in a subsequent sample interval is less than a second predetermined number.

Abstract: A frame search control circuit for a digital transmission system includes an eight bit preview store and a four stage counter. At the beginning of each frame a timing device causes the eight stored bits to be sequentially read out into a comparator for a comparison with bits from the incoming bit stream. The incoming bits are stored in the preview store simultaneously with the read out to the comparator. For an in-frame condition only the first comparison is important and the remaining comparisons are ignored. Further, a count of eight is loaded into the four stage counter which limits the count to eight allowing only eight bits from the incoming bit stream to be read into the preview store, the framing bit being read in first so as to be available for comparison at the next framing interval. For an out-of-frame condition, the timing device initiates the sequential comparison beginning with the framing interval and in this case, each comparison is important.