Abstract: A fare computer for a taxi, a freight carrier, or other use calculates the fare, display the fare as it accrues and displays visual representations of each charge contributing to the accrued fare. The fare computer is particularly suited for use in those localitites in which the taxi fare is based upon zones of travel, in accordance with a zone tariff schedule, rather than on total distance travelled. In a first mode, or ZONE TARIFF MODE, the fare computer calculates the fare from primary charge data, derived from the number of zones traversed in travelling from the origin of the trip to the destination, and secondary charge data, derived from such events as the handling of luggage or pets, extra stops, extra passengers or responding to a telephone request for passenger pick up. A display presents visual representations of the origin and destination zones and of each secondary charge contributing to the accrued fare, along with display of the total accrued fare.

Abstract: Disclosed is a binary electroexplosive device including an explosive lead and a pyrotechnic explosive which may be selectively positioned to initiate the explosive lead upon combustion of the pyrotechnic material. The pyrotechnic material is contained in an initiator assembly which may be inserted within a combination socket and housing which also holds the explosive lead facing the pyrotechnic material but spaced therefrom. Insertion of the initiator assembly within the socket completes electrical connections between a power source and a bridgewire within the initiator assembly embedded in the pyrotechnic material. In a particular embodiment shown, the electroexplosive device is utilized as a blasting cap for a well jet perforating gun wherein the gun may be completely assembled with the exception of the insertion of the initiator assembly in the socket.

Abstract: A digital computer has a master clock for generating master clock pulses at a first frequency and has a counter for counting secondary clock pulses having a frequency less than the frequency of the master clock pulses. The secondary clock pulses are counted and used in the assignment of real times to bytes of input data, and in the comparison of real times with desired output times assigned to binary output data. The input data preferably is placed in a FIFO stack and the output data in a self-sorting stack. The sorting in the output stack occurs between changes in count in the counter containing the secondary clock pulses.

Abstract: Improved processing of binary output data bytes and associated desired output times is provided. The binary output data and desired output times are placed in a self-sorting stack. Entries are time-ordered based on their respective desired output times. A real time counter is used in comparing the stack entries, one-by-one, with real time. The entry with the earliest desired output time, except in the case of an output interrupt, is compared before any other desired output time associated with a byte of output data. CPU control of the stack is not required and digital computer throughput is increased. Interruption of the CPU programming is avoided relative to transmission of outputs.

Abstract: A digital computer having a real time counter and a memory/address bus uses binary input data comprising a plurality of bits of information to generate output information in response to a program. The invention provides improved processing of the binary input data. A transition from one state to another of one or more of the bits of binary input data causes a byte of binary input data containing the bit or bits having undergone transition to be placed in an input holding register. Also, the real time at which the transition occurred is placed in a capture-time holding register. The contents of the input holding and capture-time holding registers are repetitively placed in a stack as pending input data bytes. The pending input data bytes are accessible to the computer central processing unit, as required by the program, via the memory/address bus.