Abstract: A digital computer has a master clock for generating master clock pulses at a first frequency and has a counter for counting secondary clock pulses having a frequency less than the frequency of the master clock pulses. The secondary clock pulses are counted and used in the assignment of real times to bytes of input data, and in the comparison of real times with desired output times assigned to binary output data. The input data preferably is placed in a FIFO stack and the output data in a self-sorting stack. The sorting in the output stack occurs between changes in count in the counter containing the secondary clock pulses.

Abstract: Improved processing of binary output data bytes and associated desired output times is provided. The binary output data and desired output times are placed in a self-sorting stack. Entries are time-ordered based on their respective desired output times. A real time counter is used in comparing the stack entries, one-by-one, with real time. The entry with the earliest desired output time, except in the case of an output interrupt, is compared before any other desired output time associated with a byte of output data. CPU control of the stack is not required and digital computer throughput is increased. Interruption of the CPU programming is avoided relative to transmission of outputs.

Abstract: A digital computer having a real time counter and a memory/address bus uses binary input data comprising a plurality of bits of information to generate output information in response to a program. The invention provides improved processing of the binary input data. A transition from one state to another of one or more of the bits of binary input data causes a byte of binary input data containing the bit or bits having undergone transition to be placed in an input holding register. Also, the real time at which the transition occurred is placed in a capture-time holding register. The contents of the input holding and capture-time holding registers are repetitively placed in a stack as pending input data bytes. The pending input data bytes are accessible to the computer central processing unit, as required by the program, via the memory/address bus.