Patents by Inventor Ralph M. Alfano

Ralph M. Alfano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11076016
    Abstract: A device may monitor a session involving a first user equipment and a network. The device may determine that content associated with the session is cacheable based on a characteristic of the content. The device may determine a status of the first user equipment. The device may select, based on the status and the characteristic, the first user equipment to cache content data associated with the content and transmit a cache message to the first user equipment. The cache message may be configured to cause the first user equipment to cache the content data in a local data structure of the first user equipment. The device may perform an action associated with causing the first user equipment to provide the content to a second user equipment that requests the content via the network.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: July 27, 2021
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Ralph M. Alfano, Quan Zhang, Carlo Thompson
  • Patent number: 10031989
    Abstract: Disclosed are a system and a method for integrated circuit (IC) performance modeling, wherein a design layout of an IC is analyzed to identify a first conductive shape (e.g., an internal local interconnect or contact bar shape) on a diffusion boundary shape of a semiconductor device and to also identify the first conductive shape's connectivity to any second conductive shapes (e.g., a via, via bar, or external local interconnect shapes) inside and/or outside the limits of the diffusion boundary shape. A condensed resistance model for the first conductive shape is selected from a model library based on the previously identified connectivity. The selected condensed resistance model will have a lesser number of nodes and/or resistive elements than a full resistance model for the conductive shape. The selected condensed resistance model is used to construct a condensed netlist, which is used in a combined netlist to simulate IC performance.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: July 24, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ralph M. Alfano, Arnold E. Baizley, Ning Lu, Judith H. McCullen, Cole E. Zemke
  • Publication number: 20160140273
    Abstract: Disclosed are a system and a method for integrated circuit (IC) performance modeling, wherein a design layout of an IC is analyzed to identify a first conductive shape (e.g., an internal local interconnect or contact bar shape) on a diffusion boundary shape of a semiconductor device and to also identify the first conductive shape's connectivity to any second conductive shapes (e.g., a via, via bar, or external local interconnect shapes) inside and/or outside the limits of the diffusion boundary shape. A condensed resistance model for the first conductive shape is selected from a model library based on the previously identified connectivity. The selected condensed resistance model will have a lesser number of nodes and/or resistive elements than a full resistance model for the conductive shape. The selected condensed resistance model is used to construct a condensed netlist, which is used in a combined netlist to simulate IC performance.
    Type: Application
    Filed: November 18, 2014
    Publication date: May 19, 2016
    Inventors: Ralph M. Alfano, Arnold E. Baizley, Ning Lu, Judith H. McCullen, Cole E. Zemke