Abstract: In one embodiment, a single electrical power supply is used to interchangeably power either a single motherboard or dual motherboards. Switchable output power and individual sequencing may be provided to each motherboard using FETs, such that the power supply may respond to the sequencing of each motherboard as if it were dedicated to that motherboard. In a two motherboard system, power to the first motherboard is reduced by removing some output voltages from the first motherboard. Fault circuitry may also be provided so that a power related fault on one domain does not affect operation of the other motherboard.

Abstract: A system comprising a chassis that includes a plurality of modules and a fan assembly disposed in a distal end of the chassis for drawing air in parallel pathways through the plurality of modules. At least one of the modules is a compute module having a thermal sensor disposed to sense the temperature of air flowing across a processor mounted on a motherboard. The system further comprises a fan controller receiving output from the thermal sensor, wherein the fan controller operates the fan assembly to cool the plurality of modules and maintain the thermal sensor output within an operating temperature range. The fan controller controls the fan speed according to predetermined thermal profile settings associated with one of the compute modules received in the chassis. For example, the predetermined thermal profile settings may include a minimum fan speed, a maximum fan speed, and control loop feedback settings.

Abstract: A system comprising a chassis that includes a plurality of modules and a fan assembly disposed in a distal end of the chassis for drawing air in parallel pathways through the plurality of modules. At least one of the modules is a compute module having a thermal sensor disposed to sense the temperature of air flowing across a processor mounted on a motherboard. The system further comprises a fan controller receiving output from the thermal sensor, wherein the fan controller operates the fan assembly to cool the plurality of modules and maintain the thermal sensor output within an operating temperature range. The fan controller controls the fan speed according to predetermined thermal profile settings associated with one of the compute modules received in the chassis. For example, the predetermined thermal profile settings may include a minimum fan speed, a maximum fan speed, and control loop feedback settings.

Abstract: In one embodiment, a single electrical power supply is used to interchangeably power either a single motherboard or dual motherboards. Switchable output power and individual sequencing may be provided to each motherboard using FETs, such that the power supply may respond to the sequencing of each motherboard as if it were dedicated to that motherboard. In a two motherboard system, power to the first motherboard is reduced by removing some output voltages from the first motherboard. Fault circuitry may also be provided so that a power related fault on one domain does not affect operation of the other motherboard.

Abstract: An improved system and method for performing power management on a distributed system. The system utilized to implement the present invention includes multiple servers for processing a set of tasks. The method of performing power management on a system first determines if the processing capacity of the system exceeds a predetermined workload. If the processing capacity exceeds a predetermined level, at least one of the multiple servers on the network is selected to be powered down and the tasks across the remaining servers are rebalanced. If the workload exceeds a predetermined processing capacity of the system and at least a server in a reduced power state may be powered up to a higher power state to increase the overall processing capacity of the system.

Abstract: A personal computer system is provided which includes a CPU, with the CPU being operable by a BIOS including initialization or booting instructions. The system includes a local bus and a peripheral bus. A bus interface chip, including a memory controller/peripheral bus host bridge (MC/PBHB) interconnects the local bus and the peripheral bus, and includes a latch which includes as its input clock cycles generated by the CPU. The initialization instructions of the BIOS are contained in a non-volatile ROM module located to write onto either the local bus or the peripheral bus. The MC/PBHB unit is able to decode and handle ROM cycles and is configured to either pass or not pass ROM read cycles depending upon certain control states that identify whether the ROM is located on the local bus or the peripheral bus.

Abstract: A programmable firmware store for a personal computer system includes a plurality of nonvolatile alterable electronic memories connected in a mutually paralleled circuit arrangement. The memories are connected to a controller that controls the memories to read firmware from and write firmware into the electronic memories, and to write-protect at least one of the memories. Any memory can be write-protected as initially selected by a user or technician of the system. The initial selection can be changed easily to write-protect another of the memories. The firmware in one memory includes code for checking the validity of firmware stored in another memory, and for selecting one or the other of the memories dependent upon a version code of the firmware. The controller also includes an update code for updating the firmware in a selected memory.

Abstract: An automated programmable firmware store for a personal computer system includes a plurality of nonvolatile alterable electronic memories connected in a mutually paralleled circuit arrangement. The memories are connected to a means for automatically controlling the memories to read firmware from and write firmware into the electronic memories, and to write-protect at least one of the memories. Any memory can be write-protected as initially selected by the automatic control means. The initial selection can be changed easily to write-protect another of the memories. The firmware in one memory includes code for checking the validity of firmware stored in another memory, and for selecting one or the other of the memories dependent upon a version code of the firmware. The control means also includes an update code for updating the firmware in a selected memory. The automated store further includes means for allowing the computer system to recover automatically from invalid firmware stored in one of the memories.

Abstract: A personal computer system is provided which includes a CPU, with the CPU being operable by a BIOS including initialization or booting instructions. The system includes a local bus and a peripheral bus. A bus interface chip, including a memory controller/peripheral bus host bridge (MC/PBHB) interconnects the local bus and the peripheral bus, and includes a latch which includes as its input clock cycles generated by the CPU. The initialization instructions of the BIOS are contained in a non-volatile ROM module located to write onto either the local bus or the peripheral bus. The MC/PBHB unit is able to decode and handle ROM cycles and is configured to either pass or not pass ROM read cycles depending upon certain control states that identify whether the ROM is located on the local bus or the peripheral bus.

Abstract: A personal computer system is provided which includes a CPU, with the CPU being operable by a BIOS including initialization or booting instructions. The system includes a local bus and a peripheral bus. A bus interface chip, including a memory controller/peripheral bus host bridge (MC/PBHB) interconnects the local bus and the peripheral bus, and includes a latch which includes as its input clock cycles generated by the CPU. The initialization instructions of the BIOS are contained in a non-volatile ROM module located to write onto either the local bus or the peripheral bus. The MC/PBHB unit is able to decode and handle ROM cycles and is configured to either pass or not pass ROM read cycles depending upon certain control states that identify whether the ROM is located on the local bus or the peripheral bus.