Abstract: In an example, a semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of the first conductivity type over the semiconductor substrate. A well region of a second conductivity type is in the semiconductor region. A doped region of the first conductivity type is in the well region. A doped region of the second conductivity type is in the well region. A doped region of the second conductivity type is in the semiconductor substrate at a bottom side. A doped region of the first conductivity type is in the semiconductor substrate at the bottom side. A first conductor is at a top side of the semiconductor region and a second conductor is at the bottom side. In some examples, one or more of doped regions at the bottom side is a patterned doped region.

Abstract: In an aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and forming a first semiconductor layer within the trench and along the sidewall. In an embodiment, the process can further include forming a barrier layer within the trench after forming the first semiconductor layer; forming a second semiconductor layer within the trench after forming the barrier layer, wherein within the trench, first and second portions of the second semiconductor layer contact each other adjacent to a vertical centerline of the trench; and exposing the second semiconductor layer to radiation sufficient to allow a void within second semiconductor layer to migrate toward the barrier layer. In another embodiment, after forming a semiconductor within the trench, the process can further include forming an insulating layer that substantially fills a remaining portion of the trench.

Abstract: In a general aspect, method of producing an insulated-gate bipolar transistor (IGBT) device can include forming a termination structure in an inactive region. The inactive region at least partial surround an active region. The method can also include forming a trench extending along a longitudinal axis in the active region. A first mesa can define a first sidewall of the trench, and a second mesa can define a second sidewall of the trench. The first mesa and the second mesa can be parallel with the trench. The method can further include forming, in at least a portion of the first mesa, an active segment of the IGBT device, and, forming, in at least a portion of the second mesa, an inactive segment of the IGBT device.

Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT device can also include a first mesa defined by a first sidewall of the trench and in parallel with the trench and a second mesa defined by a second sidewall of the trench and in parallel with the trench. The first mesa can include at least one active segment of the IGBT device and the second mesa can include at least one inactive segment of the IGBT device.

Abstract: In a general aspect, method of producing an insulated-gate bipolar transistor (IGBT) device can include forming a termination structure in an inactive region. The inactive region at least partial surround an active region. The method can also include forming a trench extending along a longitudinal axis in the active region. A first mesa can define a first sidewall of the trench, and a second mesa can define a second sidewall of the trench. The first mesa and the second mesa can be parallel with the trench. The method can further include forming, in at least a portion of the first mesa, an active segment of the IGBT device, and, forming, in at least a portion of the second mesa, an inactive segment of the IGBT device.

Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT can also include a first mesa defining a first sidewall of the trench and in parallel with the trench and a second mesa defining a second sidewall of the trench and in parallel with the trench. At least a portion of the first mesa can include an active segment of the IGBT device, and at least a portion of the second mesa can include an inactive segment of the IGBT device.

Abstract: An electronic device can include a semiconductor substrate having a front side and a back side; an emitter region closer to the front side than to the back side; a trench extending from a back side surface into the semiconductor substrate, wherein the trench has a sidewall and a bottom; a collector region along the back side surface and spaced apart from the bottom of the trench; a field-stop region lying along the bottom and at least a portion of the sidewall of the trench, wherein the emitter and field-stop regions have one conductivity type, and the collector region has the opposite conductivity type; and a collector terminal along the back side and including a metal-containing material, wherein the collector terminal contacts the collector region and is isolated from the field-stop region. A process of forming the electronic device does not require complex or marginal processing operations.

Abstract: Systems and methods herein are directed towards semiconductor devices and methods of manufacture thereof, including the formation of a plurality of passive trenches that act as a single passive trench and may be connected to gate electrodes and/or emitters in various embodiments.

Abstract: Systems and methods herein are directed towards semiconductor devices and methods of manufacture thereof, including the formation of a plurality of passive trenches that act as a single passive trench and may be connected to gate electrodes and/or emitters in various embodiments.

Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT can also include a first mesa defining a first sidewall of the trench and in parallel with the trench and a second mesa defining a second sidewall of the trench and in parallel with the trench. At least a portion of the first mesa can include an active segment of the IGBT device, and at least a portion of the second mesa can include an inactive segment of the IGBT device.

Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT device can also include a first mesa defined by a first sidewall of the trench and in parallel with the trench and a second mesa defined by a second sidewall of the trench and in parallel with the trench. The first mesa can include at least one active segment of the IGBT device and the second mesa can include at least one inactive segment of the IGBT device.

Abstract: A semiconductor device having a novel buried junction architecture. The semiconductor device may have three terminals and a drift region between two of the terminals. The drift region includes an upper drift layer, a lower drift layer, and a buried junction layer between the upper and lower drift layers, wherein the upper and lower drift layers have a first type of doping. The buried junction layer comprises an interspersed pattern of a first material and a second material, the first material having a second type of doping opposite the first type of doping and the second material having the first type of doping and having a different doping concentration than the upper and lower drift layers.

Abstract: A bulk acoustic wave (BAW) resonator is constructed to reduce phase and amplitude ripples in a frequency response. The BAW resonator is fabricated on a substrate 400 ?m thick or less, preferably approximately 325 ?m, having a first side and a polished second side with a peak-to-peak roughness of approximately 1000 A. A Bragg mirror having alternate layers of a high acoustic impedance material, such as tungsten, and a low acoustic impedance material is fabricated on the first side of the substrate. A BAW resonator is fabricated on the Bragg mirror. A lossy material, such as epoxy, coats the second side of the substrate opposite the first side. The lossy material has an acoustic impedance in the range of 0.01× to 1.0× the acoustic impedance of the layers of high acoustic impedance material.

Abstract: A bulk acoustic wave (BAW) resonator is constructed to reduce phase and amplitude ripples in a frequency response. The BAW resonator is fabricated on a substrate 400 ?m thick or less, preferably approximately 325 ?m, having a first side and a polished second side with a peak-to-peak roughness of approximately 1000 A. A Bragg mirror having alternate layers of a high acoustic impedance material, such as tungsten, and a low acoustic impedance material is fabricated on the first side of the substrate. A BAW resonator is fabricated on the Bragg mirror. A lossy material, such as epoxy, coats the second side of the substrate opposite the first side. The lossy material has an acoustic impedance in the range of 0.01× to 1.0× the acoustic impedance of the layers of high acoustic impedance material.

Abstract: A method of fabricating a piezoelectric resonator includes providing a bottom electrode and a piezoelectric layer coupled to the bottom electrode. A bottom metal layer of a top electrode is deposited on the piezoelectric layer. A top metal layer of the top electrode is deposited on the bottom metal layer. A photoresist layer is deposited on the top metal layer. The photoresist layer is patterned and etched. The top metal layer is patterned and etched while the etched photoresist layer remains. The bottom metal layer is patterned and etched such that an entire perimeter side surface of the top metal layer is recessed relative to a perimeter edge of the bottom metal layer. The etched photoresist layer is removed. A passivation layer is deposited on the top and bottom metal layers such that the top and bottom metal layers are isolated from a subsequent metal etch step.

Abstract: Methods of reducing phase and amplitude ripples in a BAW resonator frequency response by providing a substrate, fabricating a Bragg mirror having alternate layers of a high acoustic material and a low acoustic material on a first surface of the substrate, fabricating a BAW on the Bragg mirror, and coating a second side of the substrate opposite the first side with a lossy material having an acoustic impedance in the range of 0.01× to 1.0× the acoustic impedance of the layers of high impedance material, the second surface of the substrate being a polished surface. Various embodiments are disclosed.

Abstract: A piezoelectric layer is coupled to a bottom electrode in a method of fabricating a piezoelectric resonator. A bottom metal layer of a top electrode is deposited on the piezoelectric layer. The bottom metal layer is patterned and etched. A top metal layer of the top electrode is deposited on the etched bottom metal layer. The top metal layer is patterned and etched. An interconnect metal layer is deposited on the etched top metal layer and the piezoelectric layer such that the interconnect metal layer isolates the bottom metal layer from subsequent etch steps.

Abstract: In accordance with the present invention, accurate and easily controlled sloped walls may be formed using AlN and preferably a heated TMAH for such purpose as the fabrication of MEMS devices, wafer level packaging and fabrication of fluidic devices. Various embodiments are disclosed.

Abstract: A piezoelectric resonator includes a multi-layer top electrode configured such that a top most layer protects the underlying layers from subsequent etching, thereby preventing etch undercut of the top-most layer. In one embodiment, the multi-layer top electrode is configured as a bi-layer, so that the upper layer of the bi-layer stack protects all sides of the underlying layer from subsequent etch process steps. In an alternative embodiment, at least the perimeter of a multi-layer top electrode is completely covered with overlapping interconnect metal.

Abstract: A piezoelectric resonator include a multi-layer top electrode. The multi-layer top electrode includes at least a top metal layer and a bottom metal layer. A top metal layer edge is recessed compared to a bottom metal layer edge allowing conformal deposition of a passivation layer. The passivation layer covers and protects the underlying layers from subsequent etching, thereby preventing etch undercut of the top electrode. In some embodiments, the multi-layer top electrode is configured as a bi-layer. In other embodiments, an extra layer is configured between the top metal layer and the bottom metal layer, for example a shunt load layer.